From an analog signal to a digital device. Principles of ADC design

This article discusses the main issues regarding the operating principle of various types of ADCs. At the same time, some important theoretical calculations regarding the mathematical description of analog-to-digital conversion were left outside the scope of the article, but links are provided where the interested reader can find a more in-depth discussion of the theoretical aspects ADC operation. Thus, the article concerns itself more with understanding the general principles of operation of ADCs than with a theoretical analysis of their operation.

Introduction

As a starting point, let's define analog-to-digital conversion. Analog-to-digital conversion is the process of converting an input physical quantity into its numerical representation. An analog-to-digital converter is a device that performs such a conversion. Formally, the input value of the ADC can be any physical quantity - voltage, current, resistance, capacitance, pulse repetition rate, shaft rotation angle, etc. However, for definiteness, in what follows, by ADC we will mean exclusively voltage-to-code converters.

The concept of analog-to-digital conversion is closely related to the concept of measurement. By measurement we mean the process of comparing the measured value with some standard; during analog-to-digital conversion, the input value is compared with some reference value (usually a reference voltage). Thus, analog-to-digital conversion can be considered as a measurement of the value of the input signal, and all the concepts of metrology, such as measurement errors, apply to it.

Main characteristics of the ADC

The ADC has many characteristics, the main ones being conversion frequency and bit depth. The conversion frequency is usually expressed in samples per second (SPS), and the bit depth is in bits. Modern ADCs can have a bit width of up to 24 bits and a conversion speed of up to GSPS units (of course, not at the same time). The higher the speed and bit capacity, the more difficult it is to obtain the required characteristics, the more expensive and complex the converter. Conversion speed and bit depth are related to each other in a certain way, and we can increase the effective conversion bit depth by sacrificing speed.

Types of ADCs

There are many types of ADCs, but for the purposes of this article we will limit ourselves to considering only the following types:

Parallel conversion ADC (direct conversion, flash ADC)
Successive approximation ADC (SAR ADC)
delta-sigma ADC (charge-balanced ADC)

There are also other types of ADCs, including pipelined and combined types, consisting of several ADCs with (in general) different architecture. However, the above ADC architectures are the most representative due to the fact that each architecture occupies a certain niche in the overall speed-bit range.

ADCs of direct (parallel) conversion have the highest speed and lowest bit depth. For example, the parallel conversion ADC TLC5540 from Texas Instruments has a speed of 40MSPS with only 8 bits. ADCs of this type can have a conversion speed of up to 1 GSPS. It can be noted here that pipelined ADCs have even greater speed, but they are a combination of several ADCs with lower speed and their consideration is beyond the scope of this article.

The middle niche in the bit-rate-speed series is occupied by successive approximation ADCs. Typical values are 12-18 bits with a conversion frequency of 100KSPS-1MSPS.

The highest accuracy is achieved by sigma-delta ADCs with a bit width of up to 24 bits inclusive and a speed from SPS units to KSPS units.

Another type of ADC that has found use in the recent past is the integrating ADC. Integrating ADCs are now almost completely replaced by other types of ADCs, but can be found in older measuring instruments.

Direct conversion ADC

Direct conversion ADCs became widespread in the 1960s and 1970s, and began to be produced as integrated circuits in the 1980s. They are often used as part of “pipeline” ADCs (not discussed in this article), and have a capacity of 6-8 bits at a speed of up to 1 GSPS.

The direct conversion ADC architecture is shown in Fig. 1

Rice. 1. Block diagram Direct conversion ADC

The operating principle of the ADC is extremely simple: the input signal is supplied simultaneously to all “positive” inputs of the comparators, and a series of voltages are supplied to the “negative” ones, obtained from the reference voltage by dividing them with resistors R. For the circuit in Fig. 1 this row will be like this: (1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16) Uref, where Uref – reference voltage ADC.

Let a voltage equal to 1/2 Uref be applied to the ADC input. Then the first 4 comparators will work (if you count from below), and logical ones will appear at their outputs. The priority encoder will form a “column” of units binary code, which is captured by the output register.

Now the advantages and disadvantages of such a converter become clear. All comparators operate in parallel, the delay time of the circuit is equal to the delay time in one comparator plus the delay time in the encoder. The comparator and encoder can be made very fast, as a result the whole circuit has very high performance.

But to obtain N bits, 2^N comparators are needed (and the complexity of the encoder also grows as 2^N). Scheme in Fig. 1. contains 8 comparators and has 3 bits, to obtain 8 bits you need 256 comparators, for 10 bits - 1024 comparators, for a 24-bit ADC they would need over 16 million. However, the technology has not yet reached such heights.

successive approximation ADC

A successive approximation register (SAR) analog-to-digital converter measures the magnitude of the input signal by performing a series of sequential “weightings,” that is, comparisons of the input voltage value with a series of values generated as follows:

1. in the first step, the output of the built-in digital-to-analog converter is set to a value equal to 1/2Uref (hereinafter we assume that the signal is in the interval (0 – Uref).

2. if the signal is greater than this value, then it is compared with the voltage lying in the middle of the remaining interval, i.e., in this case, 3/4Uref. If the signal is less than the set level, then the next comparison will be made with less than half of the remaining interval (ie with a level of 1/4Uref).

3. Step 2 is repeated N times. Thus, N comparisons (“weightings”) produce N bits of the result.

Rice. 2. Block diagram of a successive approximation ADC.

Thus, the successive approximation ADC consists of the following nodes:

1. Comparator. It compares the input value and the current value of the “weighting” voltage (in Fig. 2, indicated by a triangle).

2. Digital-to-analog converter(Digital to Analog Converter, DAC). It generates a voltage “weight” based on the digital code received at the input.

3. Successive Approximation Register (SAR). It implements a successive approximation algorithm, generating the current value of the code fed to the DAC input. All of them are named after him this architecture ADC.

4. Sample/Hold scheme (Sample/Hold, S/H). For the operation of this ADC, it is fundamentally important that input voltage remained unchanged throughout the entire conversion cycle. However, “real” signals tend to change over time. The sample-and-hold circuit “remembers” the current value analog signal, and keeps it unchanged throughout the entire operating cycle of the device.

The advantage of the device is relatively high speed conversion: The conversion time of an N-bit ADC is N clock cycles. The conversion accuracy is limited by the accuracy of the internal DAC and can be 16-18 bits (24-bit SAR ADCs have now begun to appear, for example, AD7766 and AD7767).

Delta-Sigma ADC

And finally, the most interesting guy The ADC is a sigma-delta ADC, sometimes referred to in the literature as a charge-balanced ADC. The block diagram of the sigma-delta ADC is shown in Fig. 3.

Fig.3. Block diagram of a sigma-delta ADC.

The operating principle of this ADC is somewhat more complex than other types of ADC. Its essence is that the input voltage is compared with the voltage value accumulated by the integrator. Pulses of positive or negative polarity are supplied to the integrator input, depending on the comparison result. Thus, this ADC is a simple tracking system: the voltage at the integrator output “tracks” the input voltage (Fig. 4). The result of this circuit is a stream of zeros and ones at the output of the comparator, which is then passed through a digital low-pass filter, resulting in an N-bit result. LPF in Fig. 3. Combined with a “decimator”, a device that reduces the frequency of readings by “decimating” them.

Rice. 4. Sigma-delta ADC as a tracking system

For the sake of rigor of presentation, it must be said that in Fig. Figure 3 shows a block diagram of a first order sigma-delta ADC. The second order sigma-delta ADC has two integrators and two loops feedback, but will not be considered here. Those interested in this topic can refer to.

In Fig. Figure 5 shows the signals in the ADC at zero input level (top) and at Vref/2 level (bottom).

Rice. 5. Signals in the ADC at different input signal levels.

Now, without getting too complicated mathematical analysis, let's try to understand why sigma-delta ADCs have very low level own noise.

Let's consider the block diagram of the sigma-delta modulator shown in Fig. 3, and present it in this form (Fig. 6):

Rice. 6. Block diagram of a sigma-delta modulator

Here the comparator is represented as an adder that adds the continuous wanted signal and the quantization noise.

Let the integrator have a transfer function 1/s. Then, representing the useful signal as X(s), the output of the sigma-delta modulator as Y(s), and the quantization noise as E(s), we obtain the ADC transfer function:

Y(s) = X(s)/(s+1) + E(s)s/(s+1)

That is, in fact, the sigma-delta modulator is a filter low frequencies(1/(s+1)) for the useful signal, and a filter high frequencies(s/(s+1)) for noise, with both filters having the same cutoff frequency. Noise concentrated in the high-frequency region of the spectrum is easily removed by a digital low-pass filter, which is located after the modulator.

Rice. 7. The phenomenon of “displacement” of noise into the high-frequency part of the spectrum

However, it should be understood that this is an extremely simplified explanation of the phenomenon of noise shaping in a sigma-delta ADC.

So, the main advantage of the sigma-delta ADC is high precision, due to the extremely low level of self-noise. However, to achieve high accuracy, it is necessary that the cutoff frequency of the digital filter be as low as possible, many times less than the operating frequency of the sigma-delta modulator. Therefore, sigma-delta ADCs have low conversion speed.

They can be used in audio engineering, but their main use is in industrial automation for converting sensor signals, in measuring instruments, and in other applications where high accuracy is required. but high speed is not required.

A little history

The oldest mention of an ADC in history is probably the Paul M. Rainey patent, "Facsimile Telegraph System," U.S. Patent 1,608,527, Filed July 20, 1921, Issued November 30, 1926. The device depicted in the patent is actually a 5-bit direct conversion ADC.

Rice. 8. First patent for ADC

Rice. 9. Direct conversion ADC (1975)

The device shown in the figure is a direct conversion ADC MOD-4100 manufactured by Computer Labs, manufactured in 1975, assembled using discrete comparators. There are 16 comparators (they are located in a semicircle in order to equalize the signal propagation delay to each comparator), therefore, the ADC has a width of only 4 bits. Conversion speed 100 MSPS, power consumption 14 watts.

The following figure shows an advanced version of the direct conversion ADC.

Rice. 10. Direct conversion ADC (1970)

The 1970 VHS-630, manufactured by Computer Labs, contained 64 comparators, was 6-bit, 30MSPS, and consumed 100 watts (the 1975 version VHS-675 had 75 MSPS and consumed 130 watts).

Literature

W. Kester. ADC Architectures I: The Flash Converter. Analog Devices, MT-020 Tutorial.

Analog-to-digital converters are designed to convert an analog signal (usually voltage) into digital form (a sequence of digital voltage values measured at regular intervals). One of the most important parameters analog-to-digital converters is the bit depth of its output data. It is this parameter that provides the signal-to-noise ratio of the conversion and, ultimately, the dynamic range of the digital signal. They try to increase the ADC bit depth to increase the signal-to-noise ratio. The signal-to-noise ratio of an analog-to-digital converter can be determined by the following formula:

SN=N× 6 + 3.5 (dB)

Where N— the number of binary bits at the ADC output.

No less important parameter The ADC is the time at which the next digital signal sample is received at its output. To obtain simultaneously high conversion speed and large bit depth is a very difficult task, for which it was developed large number types of analog-to-digital converters. Let's consider their main characteristics and areas of application.

The fastest type of ADC are. These types of ADCs require large data streams to be transmitted, so they are transmitted in parallel. This leads to the fact that parallel ADCs have a large number external terminals. As a result, the dimensions of parallel ADC chips are quite large. Another feature of parallel ADCs is their significant current consumption. Listed disadvantages This type of ADC is a payment for the high speed of converting an analog signal into a digital form of its representation. The conversion speed in parallel ADCs reaches 500 million samples per second (500 MSPS). According to Kotelnikov's theorem, the maximum frequency of the input signal can reach 250 MHz. An example is the AD6641-500 chip from Analog Devices or the ISLA214P50 chip from Intersil.

To achieve even higher conversion rates, use parallel connection several parallel ADCs operating in turns. At the same time, in order to ensure data transfer to the processing chip, it is necessary to use several parallel buses (one for each ADC). An example of this type of analog-to-digital converters is the Maxim MAX109 ADC chip, which provides conversion speeds of up to 2.2 GSPS.

A slightly more economical type of ADC are. In these types of ADCs, digital-to-analog converters are involved in the analog-to-digital conversion process. The high speed of sending analog signal samples to the output is realized through pipeline processing. As a result, for serial-parallel FWGs, the conversion speed and the output speed of the next digital sample do not coincide. As an example, we can name the AD6645 and AD9430 microcircuits from Analog Devices.

The most common type of ADC currently is. Despite the fact that in these types of analog-to-digital converters, pipeline data processing is impossible, which means that the conversion time and the period of data output at the ADC output coincide, this type The ADC is fast enough to handle a wide range of tasks.

Currently, sample-and-hold (S&H) signal sampling and voltage-to-binary conversion (digital signal samples) are performed on a single chip. A typical circuit diagram for connecting an ADC with parallel output is shown in Figure 1.

Figure 1. Connection diagram for the ADC0804 parallel ADC

In this circuit, to begin the analog-to-digital conversion, a microprocessor or programmable logic circuit must signal the start of conversion (in this circuit this is the WR signal). After the conversion is complete ADC chip outputs a data ready signal INTR and the microprocessor can read the binary code corresponding to the input voltage. When converting a signal according to Kotelnikov’s theorem, the sampling frequency f d enters the WR input and its stability is ensured by the microprocessor.

It should be noted that when processing low-frequency signals, it is often necessary to perform both A/D conversion and D/A conversion simultaneously. In some cases, it is necessary to combine several analog channels in one chip, for example, stereo sound processing. In addition, in these types of microcircuits they include low-frequency or band-pass filters and operational amplifiers, which allows them to supply a signal directly from the microphone output to their input, and from the output to the telephone. This type of ADC/DAC chips received a special name - codecs.

Literature:

Analod-Digital Conversion, Walt Kester editor, Analog Devices, 2004. - 1138 p.
Mixed-Signal and DSP Design Techniques ISBN_0750676116, Walt Kester editor, Analog Devices, 2004. - 424 p.
High Speed System Application, Walt Kester editor, Analog Devices, 2006. - 360 p.

Together with the article "Types of analog-to-digital converters (ADCs)" read:

4. Convert analog signal to digital. Introduction to the specialty

4. Convert analog signal to digital

Digital signals

Digital telephony is now actively developing throughout the world. Digital quality telephone communication significantly higher than usual, since digital signals are less susceptible to all kinds of interference. Digital phone allows us to provide a lot additional services. There is an opportunity for the same telephone line connect seemingly completely different devices – a telephone and a personal computer. Via digital telephone network Owners of personal computers have access to data banks with a wide range of information.

Digital is coming to our homes. cable television, giving extraordinary image clarity and richness of colors; on store shelves we can see digital audio and video recording equipment that provides unique quality sound and image. What is it digital signal? We first encountered it when discussing a facsimile signal obtained from a black-and-white image that does not contain halftones.

Digital signals are telegraph and data signals generated by computers. Thus, we can say that a digital signal is a sequence of pulses. If we conditionally take the fact of the presence of a pulse as 1, and the fact of its absence as 0, then the pulse sequence can be represented as an alternation of two digits: 0 and 1. This is where the name “digital signal” comes from. A number that has only two values: 0 and 1 is called a "binary digit". Translated into English it sounds like “binary digit”. An abbreviation made up of the initial and final letters of an English phrase has come into widespread practice, i.e. the word "bit", which in English reads like bit. So, one position in a digital signal is 1 bit; it can be either 0 or 1. The eight positions in a digital signal are united by the concept byte. When transmitting digital signals, the concept is naturally introduced transmission speed is the number of bits transmitted per unit of time, most often per second.

Analog Signal Sampling

By their nature, many signals (telephone, fax, television) are not digital. These are analog, or continuous, signals. Is it possible to “translate” living human speech into the language of zeros and ones, while preserving all the rich variety of colors of the human voice, the whole gamut of human emotions? In other words, it's about how to replace continuous process sequence of numbers without losing information about the continuous process.

WITH similar problem we encounter quite often in life. If at very short intervals of time (say, after 1 s) we plot the air temperature values on a graph, we will get many points reflecting the change in temperature (Fig. 4.1). Thus, we are not dealing with a continuous curve of temperature changes, but only with its values measured at certain intervals. Essentially speaking, we described some continuous process with a sequence of decimal digits. Such a process is called sampling continuous signal. The question remains unclear how often reading values of a continuous curve should be taken in order to track all its changes. Thus, with longer periods of time between observations of air temperature, it is not possible to track all of its quick changes.

A similar approach lies in the discretization process telephone signal. If in the microphone circuit (Fig. 4.2), where the current is continuous function time, embed electronic key and periodically close it for short moments, then the current in the circuit will take the form of narrow pulses with amplitudes that repeat the shape of a continuous signal, and will represent nothing more than a discrete signal (see Fig. 4.2). The time interval through which the values of a continuous signal are counted is called sampling interval. The reciprocal quantity (let's denote it) is called the sampling frequency, or sampling rate.

Samples of a continuous signal, just like temperature samples, should be taken with such a frequency (or at such a time interval) in order to have time to track all, even the fastest, changes in the signal. Otherwise, when restoring this signal from discrete samples, part of the information will be lost and the shape of the restored signal will differ from the shape of the original one (Fig. 4.3). This means that the received sound will be perceived with distortion. To understand this issue, let's start with the vibration of the string. You touched the string, it began to vibrate and with its movement either compressed or discharged the surrounding air or, in other words, either increased or decreased its pressure. Layers of air of high and low pressure began to scatter in all directions from the oscillating body. A sound wave was formed. We see something similar when we throw stones into the water and look at the waves spreading out in circles. The crests of these waves can be compared to the area compressed air, depressions – with an area of rarefied air. The pressure of a sound wave propagating from a string varies with time according to a sinusoid. To track all its changes, obviously, it is enough to take reference values at the moments corresponding to the maxima and minima of the sinusoid, i.e. with a frequency exceeding at least twice the frequency of sound vibration. For example, if a string makes 20 vibrations/s (frequency 20 Hz), then the maximum sound pressure will be observed every 1/20 s, i.e. after 50 ms. The maxima and minima of the sound pressure curve are separated by 25 ms intervals. This means that the reading values along the curve must follow at least every 25 ms, or with a frequency of 40 readings/s (40 Hz). Typically, the reference values on the curve are taken “with a margin”: not 2 times more often than the sound fluctuates, but, say, 10 times. In this case, they convey the shape of the curve very well. An interesting case is when sound waves are emitted by two simultaneously vibrating strings. In Fig. Figure 4.4 shows three options: the second string vibrates 2, 3 and 10 times more often than the first. The pressures of two sound waves on a plate placed in their path are added. The resulting pressure graph is no longer a sinusoid. We see that the rapid changes in this curve are due to the higher frequency vibration (in this case, the vibration of the second string). In order to track all rapid changes in the resulting sound pressure, samples should be taken at a frequency that is at least twice the frequency of vibration of the second string. In the latter option, the sampling frequency must exceed 400 Hz. This means that the reading values should follow at least every 1/400 = 0.0025 s = 2.5 ms, or better yet, even more often, for example, every 0.5 ms. When studying speech, we found out that the human vocal cords play the role of strings. The highest frequency vibration of these “strings”, which, according to ITU recommendations, must still be taken into account, has a frequency of 3400 Hz. When moving from an analogue to a digital speech signal, this value is usually rounded to 4000 Hz. This means that when replacing a continuous electrical current waveform at the microphone output telephone set the latter must be taken with reference values at a frequency of 8000 Hz or, in other words, no less than every 1/8000 = 0.000125 s = 125 μs.

To restore the original signal from a discrete one, it is enough to pass the discrete signal through a low-pass filter with a cutoff frequency of the passband F and suppress all “side” spectra. The output of such a filter will be the original continuous signal. If sampling is too rare (low sampling frequency and large sampling interval), there will be an overlap of the “side” spectrum with the spectrum of the original signal. This will lead to a distortion of the shape of the original spectrum, and therefore to a difference between the reconstructed signal and the original one. On the contrary, more frequent sampling will make it easy to reconstruct a continuous signal from a discrete one using a simple low-pass filter. Thus, For distortion-free restoration of a continuous signal from a discrete one, a sampling frequency is required choose no lower than twice the width of its spectrum. For a telephone signal, as we see it, = = 8 kHz. In 1933, in the work “O bandwidth“ether” and wire in telecommunications” V.A. Kotelnikov proved a theorem that became fundamental in the theory and technology of digital communications. The essence of this theorem is that a continuous signal whose spectrum is limited by frequency F, can be completely and unambiguously reconstructed from its discrete samples taken with frequency = 2 F, i.e. at intervals. We do not present the complete mathematical formulation of the theorem, as well as its proof, but only limit ourselves to indicating the essence of the theorem.

Quantization

Let, as a result of sampling a continuous signal s(t) a sequence of narrow pulses was obtained, which represents an AIM signal. The pulse amplitudes are equal in this case to the instantaneous signal values s(t) at moments where i= 0, 1, 2, 3, ...; – pulse repetition period, or sampling interval.

Let's subject the received AIM signal to quantization by level (Fig. 4.5). To do this, the range of possible amplitude values (i.e., the range of values of the primary signal) is divided into segments called quantization steps. The boundaries of these segments are allowed for transmitting pulse amplitude values. Thus, the amplitudes of the transmitted pulses will not be equal to the instantaneous values of the primary signal, but to the nearest allowed levels. This transformation of primary signals can be called quantized pulse amplitude modulation(KAIM). A feature of the KAIM signal is that all its levels can be numbered (and their number, although large, is finite) and thereby reduce the transmission of the KAIM signal to the transmission of sequences of level numbers that this signal receives at moments. If the quantization steps are the same and do not depend on the quantization level, then the quantization is called uniform. Non-uniform quantization is possible, in which the quantization steps are different. During the quantization process, an error occurs due to the fact that the transmitted quantized signal differs from the true one. This error can be considered as a specific interference - quantization noise. The latter is a random sequence of pulses (Fig. 4.6), maximum value whose amplitude does not exceed half the quantization step. How smaller step quantization, the less noise, but the greater the number of transmitted allowed levels. The next step in signal conversion is to convert the quantized AIM signal to a digital one. This operation is called coding KAIM signal.

Coding

Let's get acquainted with one remarkable property of our number system - positionality. Let's depict some number, for example 777. In it, the same sign “7” is used 3 times, but when it is on the right, it means seven units, in the center - seven tens, on the left - seven hundreds. Thus, when writing a number, the digit may have the same outline, but the digital meanings may be different, depending on the place, position, digit on which it stands. This principle of constructing numbers is called place or positional. To write any arbitrarily large numbers, ten digits are enough! Each position, or digit, of a number has a certain “weight” (units, tens, hundreds, etc.), so the number 777 can be written as

777 = 7 × 10 2 + 7 × 10 + 7,

those. like seven hundred plus seven tens plus seven ones. If you call on algebra to help and write letters instead of numbers, you can get the following general shape number representations:

or abbreviated - through coefficients, if we omit the powers of 10:
.

The number 10 is the base of the number system. Coefficients (number of units), (number of units of the second category, i.e. tens), (number of units of the third category, i.e. hundreds), etc. can take values not exceeding the base of the system: from 0 to 9. In 1665, the French mathematician B. Pascal showed that any number can be taken as the base of the number system, which means that each number can be represented as a combination of powers of not a number 10, some other integer. Let's choose, for example, the number 7:

It is clear that the values of the coefficients should now be no more than the new foundation, i.e. 7: they can take values from 0 to 6. Let's represent the number 777 in the septenary system, expanding it in powers of the base 7:
.

If we omit the powers of the number 7, as we do when writing numbers in the decimal system, we get a septenary representation of this number: (2160)7. Here the number 7 in the index indicates the base of the system. In the fivefold positional system there are only five digits: 0, 1, 2, 3, 4. In it, the number 777 will be represented by the number of “fives”, “twenty-fives”, etc.:
.

Let's see how the number 777 is represented in the duodecimal system. Since it should have twelve digits, and we only know ten, we will have to enter two more digits, denoting 10, say, with the letter A, and 11 with the letter B. The result will be
.

As you can see, you can come up with many different positional number systems, differing only in their bases. And all of them, generally speaking, are equivalent: none of them has obvious advantages over the other! The number 2 is the smallest number that can be taken as the base of the number system. Therefore, in binary system numbering has only two digits: 0 and 1. The number in the binary system will be written like this:
.

If in the decimal system the “weight” of each position (or digit) of a number is equal to the number 10 to some degree, then in the binary system, instead of the number 10, the number 2 is used. The “weights” of the first 13 positions (bits) of a binary number have the following meanings:

Let's try to write the number (777)10, which is already familiar to us, in the binary number system, representing it in the form of an expansion in powers of two and then discarding the powers themselves when writing:

So, in the binary number system, instead of the number 777, you have to write the number 1100001001. When writing a number in the binary system, each position is occupied by a binary digit. Instead of two words “binary digit”, one word is used: “bit”. We have already mentioned that it comes from the English “bit”, made up of the initial and final letters of the phrase “binary digit”, which means “binary digit” in English. With one bit you can write only the numbers 0 and 1, two bits - numbers from 0 to 3, three bits - numbers from 0 to 7, four bits - numbers from 0 to 15, etc.

Decimal notation:

Binary notation:

To write the numbers from 0 to 1,000, you need ten bits. In the binary number system, even a relatively small number occupies many positions. How now to convert the discrete values of the microphone current into digital binary code? In the 18th century, the greatest mathematician L. Euler showed that using a set of weights 1, 2, 4, 8, and 16 kg, you can weigh any load with an accuracy of 1 kg. The load being weighed (we denote its mass by M, kg) can be represented mathematically as

Where is each coefficient a= 1, if the corresponding weight is placed on the scale, a= 0, if we do not use this weight when weighing. Thus, the weighing procedure is reduced to representing a decimal number in the binary number system. Let's explain this with an example. Suppose we need to weigh a load weighing 21 kg. Let’s first place the largest weight on the scale – weighing 16 kg. Since it does not pull the load, we will leave the weight on the bowl ( = 1) and add the next one - 8 kg. It is clear that in this case the scales with weights will outweigh the weighted scales. Let's remove this weight ( = 0) and install a weight of 4 kg. Having carried out the weighing to the end, we will see that weights weighing 16, 4 and 1 kg remain on the scales. The values of the coefficients give the five-digit binary code 10101 of the number 21. We weighed the mechanical load on mechanical scales. Considering the reference value of the current appearing at the output of the electronic key as a kind of “electrical load”, it is possible to carry out a similar weighing, but this time electronically. Such " electronic scales"was called a coder (from the English soder - encoder). Let's say the current reference value is 21 mA. The role of “electric weights” in the encoder is performed by reference currents of 16, 8, 4, 2 and 1 mA, which are generated special device. Each test—whether one or another “weight” fits or not—is performed at strictly established intervals. The entire weighing procedure must be completed before the next current reading value arrives from the electric switch (remember, for speech sounds this time is only 125 μs). So, first the sampled current value is compared with the reference value of 16 mA, and since it is greater than the reference value, a current pulse appears at the output of the encoder, which corresponds to the binary digit 1. In the next time interval, a second value of 8 mA is added to the first reference current. Now the total weight of the “electric weight” is 24 mA. This is greater than the reference value, so the second reference oscillator is turned off. During this time interval, the current pulse does not appear at the output of the encoder, which corresponds to the binary digit 0. We think that readers will easily complete the weighing procedure. Thus, during the time of weighing one sample value, the encoder generates a series of pulses that completely repeats the binary code of the sample value of the microphone current. It is impossible not to recall again another type of distortion that appears when converting the reference current value into binary code. Thus, if a sample value of 21.7 mA is encoded, the encoder will still output code 10101, as in the case of the integer value 21 mA. This is understandable, since the “weighing” was carried out with an accuracy of 1 mA - the weight of the smallest “electric weight”. This rounding of numbers in technology is called quantization, and the difference between the reference value of the current and the value typed in the binary code is the quantization error. However, distortions caused by quantization errors can be, if not completely eliminated, then at least significantly reduced. Let, for example, the smallest “electric weight” have a “weight” of 0.125 mA. Then, taking eight “weights” corresponding to 16; 8; 4; 2; 1; 0.5; 0.25; 0.125 mA, it will be possible to “weigh” the current readings with an accuracy of 0.125 mA. In this case, the number 21 will be represented by the 8-bit binary code 10101000, and the number 21.7 – by the code 10101101, where the last three digits mean the addition of 0.625 to the number 21. The use of a 12-bit binary code allows you to type very close to it instead of the number 21.7 the number is 21.6921895. Advances in the development of integrated circuit technology have made it possible to combine an electronic key and an encoder in the housing of one small microcircuit. This chip converts a continuous (often said analog) electrical quantity into binary digital code and is known as analog-to-digital converter(ADC). ADCs are available with 8-, 10- and 12-bit binary codes. It is interesting to calculate the speed of a digital stream obtained from a continuous telephone signal by sampling it at 125 μs and 8-bit encoding. The microphone current changes 8000 times per second. In an 8-bit encoder, each measured current value is represented as an 8-bit binary word. This means that every second 8000 × 8 = 64000 bits are sent to the line, i.e. the digital stream speed is 64 kbit/sec.

A code combination of 8 bits forming binary word, called byte. The characters in each code combination are separated from each other by a time interval t t, i.e. follows with frequency. This frequency is called clock. Converting continuous signal samples into binary code is called pulse code modulation (ICM). Currently, this method of obtaining digital signals from analogue ones is the most common. Transmission systems that use this signal conversion are called PCM systems. In foreign literature, the abbreviation PCM is used (from the English words pulse code modulation, which in translation means pulse code modulation).

Analog Signal Restoration

All devices designed for signal demodulation will be considered when studying specific transmission systems and the equipment included in these systems. When receiving PCM signals, to restore the analog signal, it is necessary to convert the digital signal (a sequence of binary pulses) into a quantized AIM signal (this conversion is called decoding) and then carry out the demodulation operation, i.e. extracting an analog signal from the AIM signal s(t). So, when using PCM, the following analog signal transformations are performed: at the transmission point - pulse amplitude modulation, quantization and coding; at the receiving point - decoding and demodulation of the quantized AIM signal. The analog signal received at reception differs from the transmitted one, since it is formed from quantized pulses, the amplitudes of which are equal to non-instantaneous signal values s(t), and the closest allowed values. Thus, the quantization operation introduces an irremovable error into the signal transmission process, which is smaller the more quantization levels there are. How do you find out which decimal number hidden under its entry in the binary system? The rule is simple: under each digit of a binary number its “weight” should be written down. Those “weights” that correspond to unit digits need to be added. The resulting amount will be a decimal number. Here we have the number 1001011, written in binary numbering. We proceed as stated above:

As you can see, the number that interests us is made up of one, two, eight and sixty-four (1 + 2 + 8 + 64). Obviously, it is equal to 75. Try to determine for yourself which number corresponds to its binary notation 10110011. The decoder includes a serial to parallel code converter (Fig. 4.7), at the outputs of which a set of ones and zeros appears, corresponding to the accepted code combination. Each unit (current pulse) is supplied to the input of the adder with a weight, where it increases by 2 k once. A pulse appears at the output of the adder, the amplitude of which is determined by the code combination at the input of the decoder. For example, when passing the code combination 0100110, no voltage is applied to the first, fourth, fifth and seventh inputs of the adder (no-current pulses), and a voltage is applied to the second, third and sixth inputs, which increases by 2 1, 2 2 and 2 5 times, respectively. A voltage proportional to 2 1 + 2 2 + 2 5 = 38 appears at the output of the adder, i.e. quantized AIM signal. The next step is to obtain a continuous current from the current readings. An ordinary small-capacity capacitor will help us do this, which, when briefly exposed to current (i.e., the reference value), will instantly charge and will hold the charge until the next short-term exposure. Note again that the continuous current curve reconstructed in this way will be slightly different from the one obtained at the microphone terminals: it will have flat steps between the reading values. It can be said that the process of taking samples and then reconstructing a continuous microphone current waveform is accompanied by specific distortions that can affect the quality of sound reproduction. However, in practice, to restore the current, it is not a capacitor that is used, but more complex circuits, making the shape of the restored current similar to the shape of the original current and thereby negating the effects of these distortions.

Security questions

1. What is a digital signal?
2. At what frequency should an analog signal be sampled?
3. How to determine the signal quantization error?
4. What is the principle of binary signal coding?
5. How to restore an analog signal from a digital one?

References

1. Kruk B.I., Popov G.N. ... And the mysterious world behind the curtain of numbers: Digital communication. – 2nd ed., rev. – Novosibirsk: CERIS, 2001. – 264 p.
2. Bakalov V.P., Dmitrikov V.F., Kruk B.I. Fundamentals of circuit theory: Textbook for universities; Ed. V.P. Bakalova. – M.: Radio and Communications, 2000. – 592 p.
3. Zhuravleva O.B., Kruk B.I. Discrete signals and chains: 26 questions and answers: Tutorial for distance learning. – Novosibirsk: SibGUTI, 1999. – 100 p.

Analog-to-digital converters (ADCs)- These are devices designed to convert analog signals into digital ones. For such a conversion, it is necessary to quantize the analog signal, i.e., limit the instantaneous values of the analog signal to certain levels, called quantization levels.

The ideal quantization characteristic has the form shown in Fig. 3.92.

Quantization is the rounding of an analog value to the nearest quantization level, i.e., the maximum quantization error is ±0.5h (h is the quantization step).

The main characteristics of the ADC include the number of bits, conversion time, nonlinearity, etc. The number of bits is the number of bits of the code associated with the analog value that the ADC can produce. People often talk about the resolution of an ADC, which is determined by the reciprocal of the maximum number of code combinations at the ADC output. Thus, a 10-bit ADC has a resolution of (2 10 = 1024) −1, i.e., with an ADC scale corresponding to 10V, absolute value the quantization step does not exceed 10 mV. Conversion time tp - time interval from the moment given change signal at the ADC input until the corresponding stable code appears at its output.

Typical conversion methods are the following: parallel conversion of an analog value and serial conversion.

ADC with parallel conversion of input analog signal

In the parallel method, the input voltage is simultaneously compared to n reference voltages and determined between which two reference voltages it lies. In this case, the result is obtained quickly, but the scheme turns out to be quite complex.

Operating principle of the ADC (Fig. 3.93)

When Uin = 0, since for all op-amps the voltage difference (U + − U −)< 0 (U + , U − - напряжения относительно общей точки соответственно неинвертирующего и инвертирующего входа), напряжения на выходе всех ОУ равны −Е пит а на выходах кодирующего преобразователя (КП) Z 0 , Z 1 , Z 2 устанавливаются нули. Если U вх >0.5U, but less than 3/2U, only for the lower op-amp (U + − U −) > 0 and only at its output does the +E supply voltage appear, which leads to the appearance of the following signals at the CP outputs: Z 0 = 1, Z 2 = Z l = 0. If Uin > 3/2U, but less than 5/2U, then a voltage +E supply appears at the output of the two lower op-amps, which leads to the appearance of code 010 at the outputs of the CP, etc.

Look interesting video about the operation of the ADC:

ADC with serial input signal conversion

This is a serial counting ADC, which is called a servo ADC (Fig. 3.94).
The ADC of this type uses a DAC and a reversing counter, the signal from which provides a change in the voltage at the DAC output. The circuit is configured in such a way that the voltages at the input Uin and the output of the DAC −U are approximately equal. If the input voltage Uin is greater than the voltage U at the DAC output, then the counter is switched to direct counting mode and the code at its output increases, providing an increase in the voltage at the DAC output. At the moment of equality of Uin and U, counting stops and the code corresponding to the input voltage is removed from the output of the reverse counter.

The sequential conversion method is also implemented in the ADC time - pulse conversion(ADC with linearly varying voltage generator (GLIN)).

The operating principle of the ADC under consideration, Fig. 3.95) is based on counting the number of pulses in the time period during which the linearly varying voltage (LIN), increasing from zero, reaches the input voltage level Uin. The following designations are used: CC - comparison circuit, GI - pulse generator, Kl - electronic key, Sch - pulse counter.

The moment in time t 1 marked in the timing diagram corresponds to the beginning of the measurement of the input voltage, and the moment in time t 2 corresponds to the equality of the input voltage and the GLIN voltage. The measurement error is determined by the time quantization step. Key Kl connects a pulse generator to the counter from the moment the measurement begins until the moment Uin and Uclay are equal. U Sch indicates the voltage at the meter input.

The code at the counter output is proportional to the input voltage. One of the disadvantages of this scheme is its low performance.

Double integration ADC

Such an ADC implements the method of sequential conversion of the input signal (Fig. 3.96). The following designations are used: SU - control system, GI - pulse generator, SCH - pulse counter. The operating principle of the ADC is to determine the ratio of two time periods, during one of which the input voltage Uin is integrated by an op-amp-based integrator (the voltage U and at the integrator output changes from zero to the maximum absolute value), and during the next - the integration of the reference voltage U op (U and changes from the maximum absolute value to zero) (Fig. 3.97).

Let the input signal integration time t 1 be constant, then the larger the second time period t 2 (the time period during which the reference voltage is integrated), the greater the input voltage. Key KZ is designed to set the integrator to its initial zero state. In the first of the indicated time periods, key K 1 is closed, key K 2 is open, and in the second, time period, their state is the opposite of the indicated one. Simultaneously with the closure of key K 2, pulses from the GI pulse generator begin to flow through the control circuit of the control system to the counter Sch.

The arrival of these pulses ends when the voltage at the integrator output is zero.

The voltage at the integrator output after a period of time t 1 is determined by the expression

U and (t 1) = − (1/RC) t1 ∫ 0 U input dt= − (U input t 1) / (R C)

Using a similar expression for the time interval t 2, we get

t 2 = − (R·C/U op) ·U and (t 1)

Substituting here the expression for U and (t 1), we obtain t 2 = (U in / U op) · t 1 from which U in = U oa · t 2 /t 1

The code at the counter output determines the value of the input voltage.

One of the main advantages of the ADC of this type is its high noise immunity. Random input voltage surges that occur over a short period of time have virtually no effect on the conversion error. The disadvantage of the ADC is its low speed.

The most common are ADCs of chip series 572, 1107, 1138, etc. (Table 3.3)
From the table it is clear that best performance has a parallel conversion ADC, and the worst one has a serial conversion ADC.

We invite you to watch another decent video about the operation and design of the ADC:

This article discusses the main issues regarding the operating principle of various types of ADCs. At the same time, some important theoretical calculations regarding the mathematical description of analog-to-digital conversion were left outside the scope of the article, but links are provided where the interested reader can find a more in-depth consideration of the theoretical aspects of the operation of the ADC. Thus, the article concerns itself more with understanding the general principles of operation of ADCs than with a theoretical analysis of their operation.

Introduction

Main characteristics of the ADC

Types of ADCs

There are many types of ADCs, but for the purposes of this article we will limit ourselves to considering only the following types:

Parallel conversion ADC (direct conversion, flash ADC)
Successive approximation ADC (SAR ADC)
delta-sigma ADC (charge-balanced ADC)

There are also other types of ADCs, including pipelined and combined types, consisting of several ADCs with (generally) different architectures. However, the ADC architectures listed above are the most representative due to the fact that each architecture occupies a specific niche in the overall speed-bit range.

The middle niche in the bit-rate-speed series is occupied by successive approximation ADCs. Typical values are 12-18 bits with a conversion frequency of 100KSPS-1MSPS.

The highest accuracy is achieved by sigma-delta ADCs with a bit width of up to 24 bits inclusive and a speed from SPS units to KSPS units.

Another type of ADC that has found use in the recent past is the integrating ADC. Integrating ADCs have now been almost completely replaced by other types of ADCs, but can be found in older measuring instruments.

Direct conversion ADC

The direct conversion ADC architecture is shown in Fig. 1

Rice. 1. Block diagram of direct conversion ADC

The principle of operation of the ADC is extremely simple: the input signal is supplied simultaneously to all “positive” inputs of the comparators, and a series of voltages are supplied to the “negative” ones, obtained from the reference voltage by dividing them with resistors R. For the circuit in Fig. 1 this row will be like this: (1/16, 3/16, 5/16, 7/16, 9/16, 11/16, 13/16) Uref, where Uref is the ADC reference voltage.

Let a voltage equal to 1/2 Uref be applied to the ADC input. Then the first 4 comparators will work (if you count from below), and logical ones will appear at their outputs. The priority encoder will form a binary code from a “column” of ones, which is captured in the output register.

successive approximation ADC

1. in the first step, the output of the built-in digital-to-analog converter is set to a value equal to 1/2Uref (hereinafter we assume that the signal is in the interval (0 – Uref).

3. Step 2 is repeated N times. Thus, N comparisons (“weightings”) produce N bits of the result.

Rice. 2. Block diagram of a successive approximation ADC.

Thus, the successive approximation ADC consists of the following nodes:

1. Comparator. It compares the input value and the current value of the “weighting” voltage (in Fig. 2, indicated by a triangle).

2. Digital to Analog Converter (DAC). It generates a voltage “weight” based on the digital code received at the input.

3. Successive Approximation Register (SAR). It implements a successive approximation algorithm, generating the current value of the code fed to the DAC input. The entire ADC architecture is named after it.

4. Sample/Hold scheme (Sample/Hold, S/H). For the operation of this ADC, it is fundamentally important that the input voltage remains constant throughout the conversion cycle. However, “real” signals tend to change over time. The sample-and-hold circuit “remembers” the current value of the analog signal and keeps it unchanged throughout the entire operating cycle of the device.

The advantage of the device is the relatively high conversion speed: the conversion time of an N-bit ADC is N clock cycles. The conversion accuracy is limited by the accuracy of the internal DAC and can be 16-18 bits (24-bit SAR ADCs have now begun to appear, for example, AD7766 and AD7767).

Delta-Sigma ADC

Finally, the most interesting type of ADC is the sigma-delta ADC, sometimes called charge-balanced ADC in the literature. The block diagram of the sigma-delta ADC is shown in Fig. 3.

Fig.3. Block diagram of a sigma-delta ADC.

Rice. 4. Sigma-delta ADC as a tracking system

For the sake of rigor of presentation, it must be said that in Fig. Figure 3 shows a block diagram of a first order sigma-delta ADC. The second order sigma-delta ADC has two integrators and two feedback loops, but will not be discussed here. Those interested in this topic can refer to.

In Fig. Figure 5 shows the signals in the ADC at zero input level (top) and at Vref/2 level (bottom).

Rice. 5. Signals in the ADC at different input signal levels.

Now, without delving into complex mathematical analysis, let's try to understand why sigma-delta ADCs have a very low noise floor.

Let's consider the block diagram of the sigma-delta modulator shown in Fig. 3, and present it in this form (Fig. 6):

Rice. 6. Block diagram of a sigma-delta modulator

Here the comparator is represented as an adder that adds the continuous wanted signal and the quantization noise.

Y(s) = X(s)/(s+1) + E(s)s/(s+1)

That is, in fact, the sigma-delta modulator is a low-pass filter (1/(s+1)) for the useful signal, and a high-pass filter (s/(s+1)) for noise, both filters having the same cutoff frequency. Noise concentrated in the high-frequency region of the spectrum is easily removed by a digital low-pass filter, which is located after the modulator.

Rice. 7. The phenomenon of “displacement” of noise into the high-frequency part of the spectrum

However, it should be understood that this is an extremely simplified explanation of the phenomenon of noise shaping in a sigma-delta ADC.

So, the main advantage of the sigma-delta ADC is its high accuracy, due to the extremely low level of its own noise. However, to achieve high accuracy, it is necessary that the cutoff frequency of the digital filter be as low as possible, many times less than the operating frequency of the sigma-delta modulator. Therefore, sigma-delta ADCs have low conversion speed.

A little history

Rice. 8. First patent for ADC

Rice. 9. Direct conversion ADC (1975)

The following figure shows an advanced version of the direct conversion ADC.

Rice. 10. Direct conversion ADC (1970)

The 1970 VHS-630, manufactured by Computer Labs, contained 64 comparators, was 6-bit, 30MSPS, and consumed 100 watts (the 1975 version VHS-675 had 75 MSPS and consumed 130 watts).

Literature

W. Kester. ADC Architectures I: The Flash Converter. Analog Devices, MT-020 Tutorial.