Main characteristics of digital-to-analog converters. Analog to Digital Conversion for Beginners

The simplest digital-to-analog converter (DAC) is a single-bit converter. A simple amplifier-limiter can serve as such a DAC, which can be used. One made using CMOS technology is especially suitable, since in this technology the output currents of one and zero are equal. Such a digital-to-analog converter is shown in Figure 1.

Figure 1. Schematic diagram of a single-bit digital-to-analog converter (DAC)

A single-digit DAC converts the sign of a number into analog form. For digital-to-analog conversion at a very high sampling frequency, many times higher than the Kotelnikov frequency, such a converter is quite sufficient, however, in most cases, for high-quality digital-to-analog conversion, a larger number of bits is required. It is known that a binary number is described by the following formula:

(1)

To convert digital binary code into voltage, you can use this formula directly, that is, use an analog adder. We will set the currents using resistors. If the resistors differ from each other by a factor of two, then the currents will also obey the binary law, as shown in formula (1). If a logical one is present at the output of the register, it will be converted into a current corresponding to a binary bit using a resistor. In this case, the voltage will work as a digital-to-analog converter. The circuit of a DAC operating according to the described principle is shown in Figure 2.

Figure 2. Schematic diagram of a four-bit digital-to-analog converter with summation of weight currents

In the diagram shown in Figure 2, the potential of the second terminal is zero. This is achieved by parallel negative feedback, which reduces the input impedance of the op-amp. The transfer coefficient is selected using a resistor connected from the output to the input of the operational amplifier. If unity gain is required, then this resistance must be equal to the parallel resistance of all resistors connected to the outputs of the parallel register. In the described device, the low-order current will be eight times less than the high-order current. To reduce the influence of input currents of a real operational amplifier, a resistor with a resistance equal to the parallel connection of all other resistors is connected between its non-inverting input and the common wire.

Considering that at the output of all register bits there is either a zero voltage or equal to the supply voltage, at the output of the operational amplifier the voltage will operate in the range from zero to minus the supply voltage. This is not always convenient. If you need the device to operate from a single power source, then it needs to be changed a little. To do this, apply a voltage equal to half the supply to the non-inverting input of the operational amplifier. It can be obtained from a resistive voltage divider. The zero current and the one current of the register output stage in the new circuit must match. Then the voltage at the output of the operational amplifier will vary in the range from zero to the supply voltage. The circuit of a digital-to-analog converter with unipolar power supply is shown in Figure 3.

Figure 3. Single-supply D/A converter

In the circuit shown in Figure 3, the stability of the output current and voltage is ensured by the stability of the parallel register supply voltage. However, the supply voltage of digital chips is usually very noisy. This noise will also be present in the output signal. In a multi-bit digital-to-analog converter, this is undesirable, so its output switches are powered from a highly stable, low-noise converter. Currently, such microcircuits are produced by a number of companies. Examples include the ADR4520 from Analog Devices or the MAX6220_25 from Maxim Integrated.

When manufacturing multi-bit digital-to-analog converters, it is necessary to manufacture resistors with high precision. Previously, this was achieved by laser trimming of resistors. Currently, not resistors, but current generators on field-effect transistors are usually used as current sources. The use of field-effect transistors can significantly reduce the size of the DAC chip. In this case, to increase the current, the transistors are connected in parallel. This makes it possible to achieve high accuracy of current compliance with the binary law ( i 0 , 2i 0 , 4i 0 , 8i 0, etc.). High conversion speed is achieved with low load resistance. The circuit of a digital code converter into output current operating according to the described principle is shown in Figure 4.

Figure 4. Internal DAC circuit with current summation

Naturally, the electronic switches shown in Figure 4 are also field-effect transistors. However, if you show them in a diagram, you can get confused about where the key is and where the current generator is. Since a field-effect transistor can simultaneously operate as a current generator and an electronic switch, they are often combined, and the binary law is formed using, as shown in Figure 5.

Figure 5. Internal DAC circuit with summation of equal currents

An example of a chip that uses a current summation solution is the AD7945 DAC. In it, the summation of currents is used to form the most significant bits. To work with low-order digits, . An operational amplifier is usually used to convert the output current into voltage, but its slew rate has a significant impact on the performance of the digital-to-analog converter as a whole. Therefore, the DAC circuit with an operational amplifier is used only in wideband circuits such as audio or television signal conversion.

Figure 6. Digital-to-analog converter binary code-voltage

Literature:

Together with the article “Digital-to-analog converters (DACs) with current summation” read:

http://site/digital/R2R/

http://site/digital/sigmaadc.php

Application

The DAC is used whenever it is necessary to convert a signal from a digital representation to an analogue one, for example, in CD players (Audio CD).

DAC types

The most common types of electronic DACs are:

Pulse width modulator- the simplest type of DAC. A stable source of current or voltage is periodically turned on for a time proportional to the digital code being converted, then the resulting pulse sequence is filtered by an analog low-pass filter. This method is often used to control the speed of electric motors, and is also becoming popular in Hi-Fi audio equipment;

Oversampling DAC, such as delta-sigma DACs, are based on variable pulse density. Oversampling allows you to use a DAC with a lower bit depth to achieve a higher bit depth of the final conversion; Often a delta-sigma DAC is built on the basis of a simple one-bit DAC, which is practically linear. A low-bit DAC receives a pulse signal with pulse density modulated(with a constant pulse duration, but with a variable duty cycle), created using negative feedback. Negative feedback acts as a high-pass filter for quantization noise.

Most large-bit DACs (more than 16 bits) are built on this principle due to its high linearity and low cost. The speed of the delta-sigma DAC reaches hundreds of thousands of samples per second, the bit depth is up to 24 bits. To generate a pulse density modulated signal, a simple first order or higher order delta-sigma modulator such as MASH can be used. Multi stage noise shaping). Increasing the resampling frequency softens the requirements for the output low-pass filter and improves quantization noise suppression;

Weighing type DAC, in which each bit of the converted binary code corresponds to a resistor or current source connected to a common summation point. The source current (conductivity of the resistor) is proportional to the weight of the bit to which it corresponds. Thus, all non-zero bits of the code are added to the weight. The weighing method is one of the fastest, but it is characterized by low accuracy due to the need for a set of many different precision sources or resistors and variable impedance. For this reason, weighing DACs have a maximum width of eight bits;

Ladder DAC(chain R-2R circuit). In the R-2R-DAC, values are created in a special circuit consisting of resistors with resistances R And 2R, called a constant impedance matrix, which has two types of inclusion: direct - current matrix and inverse - voltage matrix. The use of identical resistors can significantly improve accuracy compared to a conventional weighing DAC, since it is relatively simple to produce a set of precision elements with the same parameters. DACs of the R-2R type allow you to push back the limitations on bit depth. With laser trimming of resistors on one substrate, an accuracy of 20-22 bits is achieved. Most of the conversion time is spent in the operational amplifier, so it must be as fast as possible. The speed of the DAC is in the range of microseconds and below (that is, nanoseconds);

Characteristics

DACs are located at the beginning of the analog path of any system, so the parameters of the DAC largely determine the parameters of the entire system as a whole. The following are the most important characteristics of a DAC.

Maximum sampling rate- the maximum frequency at which the DAC can operate, producing the correct result at the output. According to the Nyquist-Shannon theorem (also known as the Kotelnikov theorem), to correctly reproduce an analog signal from a digital form, the sampling frequency must be no less than twice the maximum frequency in the signal spectrum. For example, to reproduce the entire human-audible audio frequency range, the spectrum of which extends up to 20 kHz, it is necessary that the audio signal be sampled at a frequency of at least 40 kHz. The Audio CD standard sets the audio sampling rate to 44.1 kHz; To reproduce this signal you will need a DAC capable of operating at this frequency. Cheap computer sound cards have a sampling rate of 48 kHz. Signals sampled at other frequencies are resampled to 48 kHz, which partially degrades the signal quality.

Monotone- the ability of the DAC to increase the analog output signal when the input code increases.

THD+N(total harmonic distortion + noise) - a measure of the distortion and noise introduced into the signal by the DAC. Expressed as a percentage of the harmonic power and noise in the output signal. An important parameter for small-signal DAC applications.

Dynamic range- the ratio of the largest and smallest signals that the DAC can reproduce, expressed in decibels. This parameter is related to the bit depth and noise threshold.

Static characteristics:
- DNL (differential nonlinearity) - characterizes how much the analog signal increment obtained by increasing the code by 1 least significant bit (LSB) differs from the correct value;
- INL (integral nonlinearity) - characterizes how much the transfer characteristic of the DAC differs from the ideal one. The ideal characteristic is strictly linear; INL shows how far the voltage at the DAC output for a given code is from the linear characteristic; expressed in minimum wage;
- gain;
- bias.

Frequency characteristics:
- SNDR (signal-to-noise ratio + distortion) - characterizes in decibels the ratio of the output signal power to the total power of noise and harmonic distortion;
- HDi (i-th harmonic coefficient) - characterizes the ratio of the i-th harmonic to the fundamental harmonic;
- THD (harmonic distortion factor) is the ratio of the total power of all harmonics (except the first) to the power of the first harmonic.

Literature

Jean M. Rabai, Anantha Chandrakasan, Borivozh Nikolic. Digital integrated circuits. Design Methodology = Digital Integrated Circuits. - 2nd ed. - M.: Williams, 2007. - 912 p. - ISBN 0-13-090996-3
Mingliang Liu. Demystifying Switched-Capacitor Circuits. ISBN 0-75-067907-7.
Phillip E. Allen, Douglas R. Holberg. CMOS Analog Circuit Design. ISBN 0-19-511644-5.

Links

Digital-to-analog converters (DACs), theory and operating principles on the Microelectronics Market website
Digital-to-analog converters for digital signal processing applications
INL/DNL Measurements for High-Speed ADCs explains how INL and DNL are calculated
Alexey Stakhov. Fibonacci Computer Part 1, Part 2, Part 3 // PCweek.ru, 2002
R-2R Ladder DAC explained contains schematics

Microcontrollers

Architecture

8-bit	MCS-51 MCS-48 PIC AVR Z8 H8 COP8 68HC08 68HC11
16-bit

DAC with pulse width modulation

Serial switched capacitor DAC

Parallel DACs

DAC with summation of weight currents
DAC on current sources
Formation of the output signal in the form of voltage
Parallel switched capacitor DAC
DAC with voltage summation

D/A Converter Interfaces

Serial Input DAC
Parallel Input DAC

DAC application

Handling signed numbers
Multipliers and dividers of functions
Attenuators and integrators on DACs
Direct digital signal synthesis systems

DAC parameters

Digital-to-analog converters

A digital-to-analog converter (DAC) is designed to convert a number, usually defined as a binary code, into a voltage or current proportional to the value of the digital code. The circuitry of digital-to-analog converters is very diverse. In Fig. Figure 1 shows a classification scheme of the DAC according to circuit characteristics. In addition, digital-to-analog converter ICs are classified according to the following criteria:

By type of output signal: with current output and voltage output
By type of digital interface: with serial input and with parallel input of input code
By number of DACs on the chip: single-channel and multi-channel
By speed: moderate and high speed

Rice. 1. DAC classification

DAC with summation of weight currents

Most parallel DAC circuits are based on the summation of currents, the strength of each of which is proportional to the weight of the digital binary bit, and only the bit currents whose value is equal to 1 should be summed. For example, suppose you want to convert a four-bit binary code into an analog current signal. The fourth, most significant digit (MSB) will have a weight of 2 3 =8, the third digit will have 2 2 =4, the second will have 2 1 =2, and the least significant digit will have 2 0 =1. If the weight of the MZR I MZR =1 mA, then I SZR =8 mA, and the maximum output current of the converter I output max = 15 mA and corresponds to code 1111 2. It is clear that the code 1001 2, for example, will correspond to I out =9 mA, etc. Consequently, it is necessary to construct a circuit that ensures generation and switching of precise weighing currents according to given laws. The simplest circuit that implements this principle is shown in Fig. 3.

WITH The resistances of the resistors are chosen so that when the switches are closed, a current corresponding to the weight of the discharge flows through them. The key must be closed when the corresponding bit of the input word is equal to one. The output current is determined by the relation

With a high bit capacity of the DAC, the current-setting resistors must be matched with high accuracy. The most stringent accuracy requirements are imposed on resistors of the highest digits, since the spread of currents in them should not exceed the current of the low-order digit. Therefore, the resistance spread in k-th digit must be less than

R/R=2 – k

From this condition it follows that the spread of the resistor resistance, for example, in the fourth digit should not exceed 3%, and in the 10th digit – 0.05%, etc.

The considered scheme, for all its simplicity, has a whole bunch of disadvantages. Firstly, for different input codes, the current consumed from the reference voltage source (RPS) will be different, and this will affect the value of the output voltage RES. Secondly, the resistance values of weight resistors can differ by thousands of times, and this makes it very difficult to implement these resistors in semiconductor ICs. In addition, the resistance of the high-order resistors in multi-bit DACs can be comparable to the resistance of the closed switch, and this will lead to a conversion error. Thirdly, in this circuit, significant voltage is applied to the open switches, which complicates their construction.

These shortcomings were eliminated in the AD7520 DAC circuit (domestic analogue of 572PA1), developed by Analog Devices in 1973, which is now essentially an industry standard (many serial DAC models are made according to it). The indicated diagram is shown in Fig. 4. MOS transistors are used here as switches.

Rice. 4. DAC circuit with switches and constant impedance matrix

In this circuit, the setting of the weighting coefficients of the converter stages is carried out by sequentially dividing the reference voltage using a resistive matrix of constant impedance. The main element of such a matrix is a voltage divider (Fig. 5), which must satisfy the following condition: if it is loaded with resistance R n, then its input impedance R inx must also take the value R n. Chain weakening coefficient = U 2 /U 1 at this load must have the specified value. When these conditions are met, we obtain the following expressions for resistances:

in accordance with Fig. 4.

Since in any position of the switches S k they connect the lower terminals of the resistors to the common circuit bus, the reference voltage source is loaded with a constant input impedance R in = R. This ensures that the reference voltage remains unchanged for any DAC input code.

According to Fig. 4, the output currents of the circuit are determined by the relations

and the input current

Since the lower terminals of the resistors 2 R matrices for any switch state S k connected to the common circuit bus through the low resistance of the closed switches, the voltages on the switches are always small, within a few millivolts. This simplifies the construction of switches and control circuits and allows the use of reference voltages from a wide range, including different polarities. Since the DAC output current depends on U op linear (see (8)), converters of this type can be used to multiply an analog signal (applying it to the reference voltage input) by a digital code. Such DACs are called multiplying(MDAC).

The accuracy of this circuit is reduced by the fact that for high-bit DACs, it is necessary to match the resistance R 0 switches with discharge currents. This is especially important for high-order keys. For example, in the 10-bit AD7520 DAC, the key MOSFETs of the six most significant bits are made different in area and their resistance R 0 increases according to the binary code (20, 40, 80, ..., 640 Ohm). In this way, the voltage drops across the switches of the first six bits are equalized (up to 10 mV), which ensures monotonicity and linearity of the DAC transient response. The 12-bit DAC 572PA2 has a differential nonlinearity of up to 0.025% (1 LSB).

Ministry of Education and Science of Ukraine

Odessa National Maritime Academy

Department of Marine Electronics

in the discipline "Systems for collecting and processing telemetric information"

"Digital-to-analog converters"

Completed:

set of FEM and RE

groups 3131

Strukov S.M.

Checked: Art. teacher

Kudelkin I.N.

Odessa – 2007

1. Introduction

2. General information

3. Serial DACs

4. Parallel DACs

5. Application of DAC

6. DAC parameters

7. List of references

INTRODUCTION

Recent decades have been due to the widespread introduction of microelectronics and computer technology into the national economy, the exchange of information with which is ensured by linear analog and digital converters (ADC and DAC).

The modern stage is characterized by large and ultra-large integrated circuits DACs and ADCs with high performance parameters: speed, small errors, multi-bit. The inclusion of an LSI DAC and ADC as a single, functionally complete unit greatly simplified their implementation in devices and installations used both in scientific research and in industry and made it possible to quickly exchange information between analog and digital devices.

General information

o By type of output signal: with current output and voltage output.

o By type of digital interface: with serial input and with parallel input of the input code.

o By the number of DACs on the chip: single-channel and multi-channel.

o By speed: moderate and high speed.

Rice. 1. DAC classification

SERIAL DACs

DAC with pulse width modulation

Very often, a DAC is part of microprocessor systems. In this case, if high speed is not required, digital-to-analog conversion can be very easily accomplished using pulse width modulation (PWM). The DAC circuit with PWM is shown in Fig. 1a.

Rice. 1. DAC with pulse width modulation

Digital-to-analog conversion is most simply organized if the microcontroller has a built-in pulse-width conversion function (for example, AT90S8515 from Atmel or 87C51GB from Intel). PWM output controls the switch S. Depending on the specified conversion bit depth (for the AT90S8515 controller, 8, 9 and 10 bit modes are possible), the controller, using its timer/counter, generates a sequence of pulses, the relative duration of which g = t And / T is determined by the relation

Where N- conversion bit depth, and D- converted code. A low-pass filter smooths out the pulses, highlighting the average voltage value. As a result, the output voltage of the converter

The considered circuit provides almost ideal linearity of the conversion and does not contain precision elements (except for the reference voltage source). Its main drawback is low performance.

Serial switched capacitor DAC

The PWM DAC circuit discussed above first converts the digital code into a time interval, which is generated using a binary counter quantum by quantum, so to obtain N- 2 bit conversions required N time quanta (cycles). The serial DAC circuit shown in Fig. 2 allows digital-to-analog conversion to be performed in significantly fewer clock cycles.

In this circuit, the capacitor capacities are WITH 1 and WITH 2 are equal. Before the conversion cycle begins, the capacitor WITH 2 is discharged with a key S 4. The input binary word is specified as a serial code. Its conversion is carried out sequentially, starting from the least significant digit d 0 . Each conversion cycle consists of two half-cycles. In the first half-cycle the capacitor WITH 1 charges to reference voltage U op at d 0 =1 by closing the key S 1 or discharges to zero at d 0 =0 by closing the key S 2. In the second half-cycle with the keys open S 1 ,S 2 and S 4 key closes S 3, which causes the charge to divide in half between WITH 1 and WITH 2. As a result we get

U 1 (0)=U out (0)=( d 0 /2)U op

While on the capacitor WITH 2 charge is maintained, capacitor charging procedure WITH 1 must be repeated for the next digit d 1 input word. After a new recharge cycle, the voltage on the capacitors will be

The transformation is performed in the same way for the remaining bits of the word. As a result for N-bit DAC output voltage will be equal to

If you want to save the result of the conversion for any long time, you should connect a UVH to the output of the circuit. After the end of the conversion cycle, you should carry out a sampling cycle, switch the UVH to storage mode and start the conversion again.

Thus, the presented circuit transforms the input code in 2 N quanta, which is significantly less than that of a PWM DAC. Here, only two matched small capacitors are required. The configuration of the analog part of the circuit does not depend on the bit depth of the converted code. However, in terms of performance, a serial DAC is significantly inferior to parallel digital-to-analog converters, which limits its scope of application.

Most parallel DAC circuits are based on the summation of currents, the strength of each of which is proportional to the weight of the digital binary bit, and only the bit currents whose value is equal to 1 should be summed. For example, suppose you want to convert a four-bit binary code into an analog current signal. The weight of the fourth, most significant digit (MSD) will be 2 3 =8, the third digit - 2 2 =4, the second - 2 1 =2 and the least significant (LSD) - 2 0 =1. If the weight of the SZR I MZR = 1 mA, then I SZR = 8 mA, and the maximum output current of the converter I out.max = 15 mA and corresponds to code 1111 2. It is clear that code 1001 2, for example, will correspond to I out = 9 mA, etc. Consequently, it is necessary to construct a circuit that ensures generation and switching of precise weighing currents according to given laws. The simplest circuit that implements this principle is shown in Fig. 3.

The resistance of the resistors is chosen so that when the switches are closed, a current corresponding to the weight of the discharge flows through them. The key must be closed when the corresponding bit of the input word is equal to one. The output current is determined by the relation

From this condition it follows that the spread of the resistor resistance, for example, in the fourth digit should not exceed 3%, and in the 10th digit - 0.05%, etc.

Ministry of Education and Science of Ukraine

Odessa National Maritime Academy

Department of Marine Electronics

in the discipline "Systems for collecting and processing telemetric information"

"Digital-to-analog converters"

Completed:

set of FEM and RE

groups 3131

Strukov S.M.

Checked: Art. teacher

Kudelkin I.N.

Odessa – 2007

1. Introduction

2. General information

3. Serial DACs

4. Parallel DACs

5. Application of DAC

6. DAC parameters

7. List of references

INTRODUCTION

General information

o By type of output signal: with current output and voltage output.

o By type of digital interface: with serial input and with parallel input of the input code.

o By the number of DACs on the chip: single-channel and multi-channel.

o By speed: moderate and high speed.

Rice. 1. DAC classification

SERIAL DACs

DAC with pulse width modulation

Rice. 1. DAC with pulse width modulation

Where N- conversion bit depth, and D- converted code. A low-pass filter smooths out the pulses, highlighting the average voltage value. As a result, the output voltage of the converter

The considered circuit provides almost ideal linearity of the conversion and does not contain precision elements (except for the reference voltage source). Its main drawback is low performance.

Serial switched capacitor DAC

U 1 (0)=U out (0)=( d 0 /2)U op

The transformation is performed in the same way for the remaining bits of the word. As a result for N-bit DAC output voltage will be equal to

Most parallel DAC circuits are based on the summation of currents, the strength of each of which is proportional to the weight of the digital binary bit, and only the bit currents whose value is equal to 1 should be summed. For example, suppose you want to convert a four-bit binary code into an analog current signal. The weight of the fourth, most significant digit (MSD) will be 2 3 =8, the third digit - 2 2 =4, the second - 2 1 =2 and the least significant (LSD) - 2 0 =1. If the weight of the SZR I MZR = 1 mA, then I SZR = 8 mA, and the maximum output current of the converter I out.max = 15 mA and corresponds to code 1111 2. It is clear that code 1001 2, for example, will correspond to I out = 9 mA, etc. Consequently, it is necessary to construct a circuit that ensures generation and switching of precise weighing currents according to given laws. The simplest circuit that implements this principle is shown in Fig. 3.

From this condition it follows that the spread of the resistor resistance, for example, in the fourth digit should not exceed 3%, and in the 10th digit - 0.05%, etc.

Rice. 4. DAC circuit with switches and constant impedance matrix

In this circuit, the setting of the weighting coefficients of the converter stages is carried out by sequentially dividing the reference voltage using a resistive matrix of constant impedance. The main element of such a matrix is a voltage divider (Fig. 5), which must satisfy the following condition: if it is loaded with resistance R n, then its input resistance R in must also take the value R n. The chain weakening coefficient a=U 2 /U 1 at this load must have a given value. When these conditions are met, we obtain the following expressions for resistances:

With binary coding a =0.5. If we put R n =2R, then R s =R and R p =2R in accordance with Fig.4.

Since in any position of the switches S k they connect the lower terminals of the resistors to the common circuit bus, the reference voltage source is loaded with a constant input resistance Rin =R. This ensures that the reference voltage remains unchanged for any DAC input code.

According to Fig. 4, the output currents of the circuit are determined by the relations

and the input current

Since the lower terminals of the resistors 2R of the matrix, in any state of the switches S k, are connected to the common circuit bus through the low resistance of the closed switches, the voltages on the switches are always small, within a few millivolts. This simplifies the construction of switches and control circuits and allows the use of reference voltages from a wide range, including different polarities. Since the output current of the DAC depends linearly on U op (see (8)), converters of this type can be used to multiply the analog signal (applying it to the reference voltage input) by a digital code. Such DACs are called multiplying DACs (MDACs).

The accuracy of this circuit is reduced by the fact that for DACs with a high bit capacity, it is necessary to match the resistance R 0 of the switches with the bit currents. This is especially important for high-order keys. For example, in the 10-bit AD7520 DAC, the key MOSFETs of the six most significant bits are made different in area and their resistance R0 increases according to the binary code (20, 40, 80, : , 640 Ohms). In this way, the voltage drops across the switches of the first six bits are equalized (up to 10 mV), which ensures monotonicity and linearity of the DAC transient response. The 12-bit DAC 572PA2 has a differential nonlinearity of up to 0.025% (1 LSB).

DACs based on MOS switches have relatively low performance due to the large input capacitance of the MOS switches. The same 572PA2 has a settling time of the output current when changing the input code from 000...0 to 111...1, equal to 15 μs. The Burr-Braun 12-bit DAC7611 has an output voltage settling time of 10 µs. At the same time, DACs based on MOS switches have minimal power consumption. The same DAC7611 consumes only 2.5 mW. Recently, DAC models of the type discussed above have appeared with higher performance. Thus, the 12-bit AD7943 has a current settling time of 0.6 μs and a power consumption of only 25 μW. Low self-consumption allows such micro-power DACs to be powered directly from the reference voltage source. Moreover, they may not even have a pin for connecting an ION, for example, AD5321.

DAC on current sources

DACs based on current sources have higher accuracy. Unlike the previous version, in which the weight currents are formed by resistors of relatively low resistance and, as a result, depend on the resistance of the switches and the load, in this case the weight currents are provided by transistor current sources with high dynamic resistance. A simplified circuit of a DAC using current sources is shown in Fig. 6.

Rice. 6. DAC circuit on current sources

The weight currents are generated using a resistive matrix. The potentials of the bases of the transistors are the same, and in order for the potentials of the emitters of all transistors to be equal, the areas of their emitters are made different in accordance with the weighting coefficients. The right resistor of the matrix is not connected to the common bus, as in the diagram in Fig. 4, and to two identical transistors VT 0 and VT n connected in parallel, as a result of which the current through VT 0 is equal to half the current through VT 1. The input voltage for the resistive matrix is created using the reference transistor VT op and the operational amplifier OU1, the output voltage of which is set such that the collector current of the transistor VT op takes the value I op. Output current for N-bit DAC

Typical examples of DACs based on current switches with bipolar transistors as switches are the 12-bit 594PA1 with a settling time of 3.5 μs and a linearity error of no more than 0.012% and the 12-bit AD565, which has a settling time of 0.2 μs with the same linearity error. The AD668 has even higher performance, with a settling time of 90 ns and the same linearity error. Among the new developments, we can note the 14-bit AD9764 with a settling time of 35 ns and a linearity error of no more than 0.01%. Bipolar differential stages in which transistors operate in active mode are often used as current switches S k. This allows the settling time to be reduced to a few nanoseconds. The current switch circuit for differential amplifiers is shown in Fig. 7.

Differential cascades VT 1 -VT 3 and VT" 1 -VT" 3 are formed from standard ESL valves. The current I k flowing through the collector terminal of the output emitter follower is the output current of the cell. If a high level voltage is applied to the digital input D k, then transistor VT 3 opens and transistor VT" 3 closes. The output current is determined by the expression

The accuracy increases significantly if the resistor R e is replaced by a direct current source, as in the circuit in Fig. 6. Thanks to the symmetry of the circuit, it is possible to generate two output currents - direct and inverse. The fastest models of such DACs have ESL input levels. An example is the 12-bit MAX555, which has a settling time of 4 ns to the 0.1% level. Since the output signals of such DACs cover the radio frequency range, they have an output impedance of 50 or 75 ohms, which must be matched to the characteristic impedance of the cable connected to the output of the converter.

DAC APPLICATION

Schemes for the use of digital-to-analog converters relate not only to the field of code-to-analog conversion. Using their properties, you can determine the products of two or more signals, build function dividers, analog links controlled by microcontrollers, such as attenuators, integrators. Signal generators, including arbitrary waveforms, are also an important area of application for DACs. Below are some signal processing circuits that include D-A converters.

Handling signed numbers

Until now, when describing digital-to-analog converters, input digital information was represented in the form of natural numbers (unipolar). Processing integers (bipolar) has certain features. Typically, binary integers are represented using two's complement code. In this way, using eight digits, you can represent numbers in the range from -128 to +127. When entering numbers into the DAC, this range of numbers is shifted to 0...255 by adding 128. Numbers greater than 128 are considered positive, and numbers less than 128 are considered negative. The average number 128 corresponds to zero. This representation of signed numbers is called a shifted code. Adding a number that is half the full scale of a given bit (in our example it is 128) can be easily done by inverting the most significant (sign) bit. The correspondence of the considered codes is illustrated in Table. 1.

Table 1

Relationship between digital and analog quantities

To obtain an output signal with the correct sign, it is necessary to reverse shift by subtracting the current or voltage that is half the scale of the converter. This can be done in different ways for different types of DACs. For example, with DACs based on current sources, the range of variation of the reference voltage is limited, and the output voltage has a polarity opposite to the polarity of the reference voltage. In this case, the bipolar mode is most simply implemented by including an additional bias resistor R cm between the DAC output and the reference voltage input (Fig. 8a). Resistor R cm is manufactured on an IC chip. Its resistance is chosen such that the current I cm is half the maximum value of the DAC output current.

In principle, the problem of output current bias can be solved similarly for DACs based on MOS switches. To do this, you need to invert the reference voltage, and then generate a bias current from -U op, which should be subtracted from the DAC output current. However, to maintain temperature stability, it is better to ensure that the bias current is generated directly in the DAC. To do this, in the diagram in Fig. 8a, a second operational amplifier is introduced and the second output of the DAC is connected to the input of this op-amp (Fig. 8b).

Second DAC output current,

At the input of op-amp1, the current I" out is summed with the current I mr, corresponding to the unit of the least significant digit of the input code.

The total current is inverted. The current flowing through the feedback resistor R os OU2 is

and when

In the case of N=8, this coincides with the data in table up to a factor of 2. 6, taking into account the fact that for a converter based on MOS switches the maximum output current

If resistors R2 are well matched in resistance, then an absolute change in their value with temperature fluctuations does not affect the output voltage of the circuit.

For digital-to-analog converters with an output signal in the form of voltage, built on an inverse resistive matrix (see Fig. 9), the bipolar mode can be more easily implemented (Fig. 8c). Typically, such DACs contain an on-chip output buffer amplifier. To operate the DAC in a unipolar connection, the free terminal of the lower resistor R in the circuit is not connected, or is connected to a common point in the circuit to double the output voltage. To operate in a bipolar connection, the free output of this resistor is connected to the reference voltage input of the DAC. In this case, the op-amp operates in differential connection and its output voltage

As mentioned above, D-A converters based on MOS switches allow changes in the reference voltage within a wide range, including a change in polarity. The DAC output voltage is proportional to the product of the reference voltage and the input digital code. This circumstance makes it possible to directly use such DACs to multiply an analog signal by a digital code.

When the DAC is connected unipolarly, the output signal is proportional to the product of a bipolar analog signal and a unipolar digital code. Such a multiplier is called a two-quadrant multiplier. When the DAC is connected bipolarly (Fig. 8b and 8c), the output signal is proportional to the product of a bipolar analog signal and a bipolar digital code. This circuit can work as a four-quadrant multiplier.

Dividing the input voltage by a digital scale M D =D/2 N is performed using a two-quadrant divider circuit (Fig. 9).

In the diagram in Fig. 9a, a MOS switch converter with a current output operates as a voltage-to-current converter controlled by the D code and included in the op-amp feedback circuit. The input voltage is applied to the free terminal of the DAC feedback resistor located on the IC chip.

In this circuit, the output current of the DAC is

that when the condition R os = R is fulfilled, it gives

It should be noted that with the code "all zeros" the feedback is opened. This mode can be prevented by either disabling such code in software, or by connecting a resistor with a resistance equal to R·2 N+1 between the output and the inverting input of the op-amp.

A divider circuit based on a DAC with a voltage output built on an inverse resistive matrix and including a buffer op-amp is shown in Fig. 9b. The output and input voltages of this circuit are related by the equation

It follows .

In this circuit, the amplifier is covered by both positive and negative feedback. For negative feedback to prevail (otherwise the op-amp will turn into a comparator), condition D must be met<2 N-1 или M D <1/2. Это ограничивает значение входного кода нижней половиной шкалы.

DAC PARAMETERS

With a sequential increase in the values of the input digital signal D(t) from 0 to 2 N -1 through the least significant unit (EMP), the output signal U out (t) forms a stepped curve. This dependence is usually called the DAC conversion characteristic. In the absence of hardware errors, the midpoints of the steps are located on the ideal straight line 1 (Fig. 10), which corresponds to the ideal transformation characteristic. The actual transformation characteristic may differ significantly from the ideal one in terms of the size and shape of the steps, as well as their location on the coordinate plane. There are a number of parameters to quantify these differences.

Rice. 10 Static characteristics of DAC conversion

Static parameters

Resolution - increment U out when converting adjacent values D j, i.e. different on the EMR. This increment is the quantization step. For binary conversion codes, the nominal value of the quantization step is h=U psh /(2 N -1), where U psh is the nominal maximum output voltage of the DAC (full scale voltage), N is the bit capacity of the DAC. The higher the bit depth of the converter, the higher its resolution. Full scale error is the relative difference between the actual and ideal values of the conversion scale limit in the absence of zero offset.

It is the multiplicative component of the total error. Sometimes indicated by the corresponding EMP number.

Zero offset error - the value of U out when the DAC input code is zero. It is an additive component of the total error. Typically stated in millivolts or as a percentage of full scale:

Nonlinearity is the maximum deviation of the actual conversion characteristic U out (D) from the optimal one (line 2 in Fig. 10). The optimal characteristic is found empirically so as to minimize the value of the nonlinearity error. Nonlinearity is usually defined in relative units, but in the reference data it is also given in the EMP. For the characteristics shown in Fig. 10

Differential nonlinearity is the maximum change (taking into account the sign) of the deviation of the actual transformation characteristic U out (D) from the optimal one when moving from one input code value to another adjacent value. Usually defined in relative units or in EMR. For the characteristics shown in Fig. 10,

The monotonicity of the conversion characteristic is an increase (decrease) in the output voltage of the DAC U out with an increase (decrease) in the input code D. If the differential nonlinearity is greater than the relative quantization step h/U psh, then the converter characteristic is non-monotonic.

The temperature instability of a DA converter is characterized by the temperature coefficients of full scale error and zero offset error.

Full scale and zero offset errors can be corrected by calibration (tuning). Nonlinearity errors cannot be eliminated by simple means.

The dynamic parameters of the DAC are determined by the change in the output signal when the input code changes abruptly, usually from the value “all zeros” to “all ones” (Fig. 11).

Rice. 11. DAC transient response

Establishment time is the time interval from the moment the input code changes (in Fig. 11 t=0) until the moment when the equality is satisfied for the last time

|U out -U psh |=d/2,

with d/2 usually corresponding to EMP.

Slew rate - the maximum rate of change of U out (t) during the transient process. It is defined as the ratio of the increment DU out to the time Dt during which this increment occurred. Usually specified in the technical specifications of a DAC with a voltage output signal. For a DAC with a current output, this parameter largely depends on the type of output op-amp.

For voltage-output multiplying DACs, the unity gain frequency and power bandwidth are often specified, which are largely determined by the properties of the output amplifier.

LIST OF REFERENCES USED

1. Federkov B.G., Telets V.A., DAC and ADC microcircuits: operation, parameters, application. M.: Energoizdat, 1990. –320 p.

2. Valakh V.V., Grigoriev V.F., High-speed ADCs for measuring the shape of random signals M.: Instruments and experimental techniques. 1987. No. 4 p.86-90

3. High-speed integrated circuits DAC and ADC and measurement of their parameters. Edited by Marcinkavyuches. M.: Radio and communications. 1988 –224 pp.©

Main characteristics of digital-to-analog converters. Analog to Digital Conversion for Beginners

Application

DAC types

Characteristics

See also

Literature

Links

Digital-to-analog converters

DAC with summation of weight currents

INTRODUCTION

INTRODUCTION