What are the parameters of transistors in cmos chips. How does a kmop transistor work?

The fundamental difference between CMOS circuits and nMOS technology is the absence of active resistances. A pair of transistors with different types channel. Transistors with a p-type channel are connected by the substrate to the power source, so the formation of a channel in them will occur when the potential difference between the substrate and the gate is sufficiently large, and the potential at the gate must be negative relative to the substrate. This state is ensured by applying ground potential to the gate (i.e. logical 0). Transistors with an n-type channel are connected by the substrate to ground, so the formation of a channel in them will occur when a power source potential is applied to the gate (i.e. logical 1). Simultaneous supply to such pairs of transistors with different types channels of logical zero or logical one leads to the fact that one transistor of the pair will necessarily be open and the other closed. Thus, conditions are created for connecting the output either to a power source or to ground.

So, in the simplest case, for the inverter circuit (Fig. 16.10) at A = 0, transistor VT1 will be open and VT2 will be closed. Consequently, the output of circuit F will be connected through channel VT1 to the power source, which corresponds to the logical one state: F=1. At A=1, transistor VT1 will be closed (the gate and substrate have the same potentials), and VT2 will be open. Therefore, the output of circuit F will be connected through the channel of transistor VT2 to ground. This corresponds to a logical zero state: F=0.

Logical addition (Fig. 16.11) is carried out due to serial connection p-channels of transistors VT1 and VT2. When at least one unit is supplied, a single channel does not form for these transistors. At the same time, thanks to the parallel connection of VT3 and VT4, the corresponding transistor at the bottom of the circuit is opened, ensuring the connection of output F to ground. It turns out F=0 when at least one logical 1 is applied - this is the OR-NOT rule.

The NAND function is carried out through a parallel connection of VT1 and VT2 in the upper part of the circuit and a serial connection of VT3 and VT4 in the lower part (Fig. 16.12). When applying zero to at least one input single channel on VT3 and VT4 is not generated, the output will be disconnected from ground. At the same time, at least one transistor in the upper part of the circuit (to the gate of which a logical zero is applied) will provide connection of the output F to the power source: F = 1 when at least one zero is applied - the AND-NOT rule.

Brief summary

Depending on the element base, there are various technologies produced by IC. The main ones are TTL on bipolar transistors and nMOS and CMOS on field effect transistors.

Key terms

nMOS technology field effect transistors with an n-type induced channel.

3-state buffer– output part TTL circuits, providing the possibility of transition to the third, high-impedance state.

CMOS technology- IC production technology based on field effect transistors with channels of both types of electrical conductivity.

Open collector– an option for implementing the buffer part of TTL elements without a resistor in the load circuit, which is removed outside the circuit.

Schemes with active load – TTL circuits in which the state of the buffer circuit is determined by the state of not one, but two transistors.

Transistor-transistor logic– IC production technology based on bipolar transistors.

Accepted abbreviations

CMOS – complementary, metal, oxide, semiconductor

Practice kit

Exercises for lecture 16

Exercise 1

Option 1 for exercise 1.Draw a circuit of a 3-input NOR element using nMOS technology.

Option 2 for exercise 1.Draw a circuit of a 3-input NAND element using nMOS technology.

Option 3 for exercise 1.Draw a circuit of a 4-input NOR element using nMOS technology.

Exercise 2

Option 1 for exercise 2.Draw a circuit of a 3-input NOR gate using CMOS technology.

Option 2 for exercise 2.Draw a circuit of a 3-input NAND gate using CMOS technology.

Option 3 for exercise 2.Draw a circuit of a 4-input NOR gate using CMOS technology.

Exercise 3

Option 1 for exercise 3.Draw a circuit of a 3-input NOR element using TTL technology.

Option 2 for exercise 3.Draw a diagram of a 3-input NAND element using TTL technology.

Option 3 for exercise 3.Draw a circuit of a 4-input NOR element using TTL technology.

Exercise 4

Option 1 for exercise 4.Draw a circuit of a 3-input OR element using nMOS technology.

Option 2 for exercise 4.Draw a circuit of a 3-input AND element using nMOS technology.

Option 3 for exercise 4.Draw a circuit of a 4-input OR element using nMOS technology.

Exercise 5

Option 1 for exercise 5.Draw the circuit of a 3-input OR gate using CMOS technology.

Option 2 for exercise 5.Draw a circuit diagram of a 3-input AND element using CMOS technology.

Option 3 for exercise 5.Draw the circuit of a 4-input OR gate using CMOS technology.

Exercise 6

Option 1 for exercise 6.Draw a circuit of a 3-input OR element using TTL technology.

Option 2 for exercise 6.Draw a circuit of a 3-input AND element using TTL technology.

Option 3 for exercise 6.Draw a circuit of a 4-input OR element using TTL technology.

Exercise 7

Option 1 for exercise 7.Draw a diagram of a 2I-OR-NOT element using TTL technology.

Option 2 for exercise 7.Draw a diagram of a 2I-OR-NOT element using CMOS technology.

Option 3 for exercise 7.Draw a diagram of a 2AND-OR-NOT element using nMOS technology.

Exercise 8

Option 1 for exercise 8.Draw a circuit of a 3-input NOR gate with a 3-state buffer.

Option 2 for exercise 8.Draw the circuit of a 3-input NAND gate with an open collector.

Option 3 for exercise 8.Draw a circuit of a 3-input OR gate with a 3-state buffer.

The main generic feature of TTL is the use of bipolar transistors, and the structure is only p-p-p. CMOS, as its name implies, is based on field-effect transistors with an insulated gate of the MOS structure, and complementary, that is, of both polarities - both with a w- and a /^-channel. The circuit design of basic TTL and CMOS logic elements is shown in Fig. 15.1. In the West, they are also called valves - we will see how this name can be justified at the end of the chapter.

We have already drawn the input multi-emitter TTL transistor in Chapter I - it can have as many emitters as you like (in practice, up to eight), and the element will then have the corresponding number of inputs. If any of the emitters of transistor VT1 is shorted to ground, then the transistor will open, and phase-shifting transistor VT2 (we are familiar with its operation from Fig. 6.8) will close. Accordingly, the output transistor VT3 will open and VT4 will close, the output will be a high logical level, or a logical one level. If all the emitters are connected to a high potential (or simply “hang” in the air), then the situation will be the opposite - VT2 will open with current through the base-collector junction VT1 (this switching on of the transistor is called “inverse”), and the output will be set to zero due to the open transistor VT4. Such a TTL element will perform the “AND-NOT” function (logical zero at the output only when all inputs are ones).

TTL

The output stage of the TTL element is a kind of complementary (“push-pull”) class B stage, familiar to us from analog amplifiers (see Fig. 8.2). However, reproducing pnp transistors turned out to be too difficult for TTL technology, which is why such a cascade is also called pseudo-complementary - the upper transistor VT3 operates in emitter follower mode, and the lower one in a common emitter circuit.

Rice. 15.1. Circuits of basic TTL and CMOS elements

By the way, we note that due to the unavailability of p-w-p transistors, reproducing the “OR” circuit for TTL technology turned out to be a tough nut to crack, and its circuit design differs quite significantly from that shown in Fig. 15.1 basic diagram of the “AND-NOT” element.

Notes in the margins

In the early days of transistor technology, pseudo-complementary stages similar to the TTL output stage were used - oh horror! - to enhance sound. This construction gave rise to numerous attempts to adapt logic elements, which, in essence, are an amplifier with a fairly large (several tens) gain, to amplify analog signals. Needless to say, the results were quite disastrous, even with a CMOS element that is built much more symmetrically.

As can be seen from the diagram, the TTL element is significantly asymmetrical in both inputs and outputs. At the input, the logical zero voltage should be quite close to ground; when the voltage at the emitter is about 1.5 V (with a standard TTL supply of 5 V), the input transistor is already turned off. Moreover, when applying zero, it is necessary to ensure the removal of a fairly significant base-emitter current - about 1.6 mA for a standard element, which is why TTL elements are always specified maximum amount simultaneously connected to the output of other such elements (standard - no more than a dozen). At the same time, a logical one may not be supplied to the inputs at all. In practice, however, it should be supplied - according to the rules, unused TTL inputs must be connected to the power supply through 1 kOhm resistors.

Things are even worse at the output: the logical zero voltage is provided open transistor and indeed quite close to zero - even with a load in the form of a dozen inputs of other similar elements, it does not exceed 0.5 V, and the standards for a TTL signal stipulate a value of no more than 0.8 V. But the voltage of the logical unit is quite far from power supply and with a power supply of 5 V in the best case (without load) from 3.5 to 4 V, in practice the standards stipulate a value of 2.4 V.

This balancing of tenths of a volt (zero voltage 0.8 V, switching threshold voltage from 1.2 to 2 V, unity voltage 2.4 V) leads to the fact that all TTL microcircuits can operate in a rather narrow range of supply voltages - almost from 4.5 to 5.5 V, many even from 4.75 to 5.25 V, that is 5 V ±5%. Maximum permissible voltage power supply ranges from 6 to 7 V for different TTL series, and when it is exceeded they usually burn with a clear flame. A low and asymmetrical relative to the power supply threshold of the element also leads to poor noise immunity.

The largest (and even more serious than the others) disadvantage of TTL is its high consumption - up to 2.5 mA per such element, this does not take into account the flowing currents at the input and load consumption at the output. So one has to wonder why TTL chips containing many basic elements, such as counters or registers, do not require a cooling radiator. The combination of low noise immunity with high consumption is a rather explosive mixture, and when wiring boards with TTL microcircuits, you have to install a decoupling capacitor on each case. All of the above together would have long ago forced us to abandon TTL technology altogether, but until some time they had one undeniable advantage: high performance, which for the basic element in the form shown in Fig. 15.1, can reach tens of megahertz.

IN further development TTL followed the line of reducing consumption and improving electrical characteristics, mainly through the use of the so-called. Schottky junctions, on which the voltage drop can be 0.2-0.3 V instead of the usual 0.6-0.7 V (TTLSh technology, designated by the letter S in the name of the series, the domestic analogue is the 531 and 530 series). The basic technology, which formed the basis of the 74 series, widespread in the 1960s and 70s, without additional letters in the designation (analogues are the famous domestic series 155 and 133), is now practically not used. TTL chips can now be selected from the low-power 74LSxx series (555 and 533 series) or the high-speed 74Fxx series (1531 series). Moreover, the consumption of the latter is almost equal to the consumption of the old basic series at higher (up to 125 MHz) speed, but for the former it’s the other way around - the performance is maintained at the base level, but power consumption is reduced by three to four times.

CMOS

CMOS elements are much closer to the idea of ​​what an ideal logic element should be. To begin with, as can be seen from Fig. 15.1, they are practically symmetrical, both in input and output. An open field-effect transistor at the output (either a /?-type for a logical one, or a -type for a logical zero) is in fact, as we know.

just resistance, which for conventional CMOS elements can range from 100 to 300 Ohms (by “conventional” or “classical” CMOS we mean here the 4000A or 4000V series, see below). For additional symmetry, two inverters similar to the one shown in Fig. are usually placed in series at the output. 15.1 on the right (is it a pity, perhaps, for transistors if consumption does not increase?). Therefore, the output is not affected by the fact that in the lower arm for the “AND-NOT” circuit there are two such transistors in series.

For the “OR” circuit, such transistors will be in the upper arm - it is completely symmetrical to the “AND” circuit, which is also a plus of CMOS technology compared to TTL. Please also note that the output stage of the inverter is not built according to a “push-pull” stage circuit, that is, these are not flow voltage followers, but transistors in a circuit with a common source, connected by drains, which allows you to obtain an additional voltage gain.

In practice, the design features of the element lead to the fact that in CMOS microcircuits:

At the unloaded output, the logic one voltage is almost equal to the supply voltage, and the logic zero voltage is almost equal to the ground potential;

The switching threshold is close to half the supply voltage;

The inputs consume virtually no current, since they are isolated gates of MOS transistors;

In static mode, the entire element also does not consume current from the power supply.

From the last position it follows that a circuit of any degree of complexity, built using CMOS elements, in a “frozen” state and even at low operating frequencies, not exceeding a dozen or two kilohertz, consumes practically no energy! From this it is clear how such tricks as wrist watch, which can run on a tiny battery for years, or the sleep mode of microcontrollers, in which they consume from 1 to 50 μA for all tens of thousands of logical elements that make them up.

Another consequence of the above features is exceptional noise immunity, reaching half the supply voltage. But that's not all the benefits. CMOS microcircuits of the “classic” series can operate in the supply voltage range from 2 to 18 V, and modern high-speed ones - from 2 to 7 V. The only thing that happens in this case is

When the power supply drops quite sharply, performance drops and some other characteristics deteriorate.

In addition, CMOS output transistors, like any other field-effect transistors, when overloaded (for example, in short circuit) work as current sources - at a supply voltage of 15 V this current will be about 30 mA, at 5 V - about 5 mA. Moreover, this, in principle, can be a long-term operating mode of such elements; the only thing that needs to be checked is whether the value of the total permissible current through the power output, which is usually about 50 mA, is not exceeded. That is, you may have to limit the number of outputs simultaneously connected to a low-impedance load. Naturally, there is no talk about logical levels in this mode, only about the inflowing or outflowing current.

And here we come to the main disadvantage of “classical” CMOS technology - low TTL comparison speed. This is due to the fact that the insulated gate of the MOS transistor is a capacitor with a fairly large capacitance - in the base element up to 10-15 pF. In combination with the output resistive impedance of the previous circuit, such a capacitor forms a filter low frequencies. Usually, not just frequency properties are considered, but the delay time of signal propagation to one logic element. The delay occurs due to the fact that the front of the signal is not strictly vertical, but inclined, and the output voltage will only begin to increase (or decrease) when the input voltage reaches a significant value (ideally, half the supply voltage). The delay time could reach 200-250 ns in early CMOS series (compare - the basic TTL series has only 7.5 ns). In practice, with a supply voltage of 5 V, the maximum operating frequency“classical” CMOS does not exceed 1-3 MHz - try to build a rectangular signal generator using logic elements using any of the circuits that will be discussed in Chapter 16, and you will see that already at a frequency of 1 MHz the signal shape will more closely resemble a sine wave than a rectangle .

Another consequence of the presence of a high input capacitance is that when switching, a current pulse appears to recharge this capacitance, that is, the higher the operating frequency, the more the microcircuit consumes, and it is believed that at maximum operating frequencies its consumption can be compared with the consumption of TTL (according to at least, TTL series 74LS). The matter is further aggravated by the fact that, due to prolonged pulse fronts, the element is quite long time is in the active state when both output transistors are slightly open (that is, the so-called “through current” effect occurs).

This same prolongation of the fronts in combination with a high-impedance input leads to a decrease in noise immunity when switching - if high-frequency interference “sits” at the signal front, this can lead to multiple switching of the output, as was the case with a comparator (see Chapter 13). For this reason, specifications for microcircuits often indicate the desired maximum duration of the control signal edges.

However, in modern CMOS, in contrast to “classical” ones, most of the disadvantages associated with low performance have been overcome (although by reducing the permissible power supply range). More details about the CMOS series are described below, but for now a few more words about the features of these microcircuits.

The unused inputs of the CMOS element must be connected somewhere - either to ground or to power (no resistors are required, since the input does not consume current), or combined with an adjacent input - otherwise interference at such a high-impedance input will completely disrupt the operation of the circuit. Moreover, in order to reduce consumption, this should also be done in relation to unused elements in the same case (but not to all unused terminals, of course). The “bare” CMOS input, due to its high resistance, can also be the reason for the increased “mortality” of chips when exposed to static electricity, however, in practice, the inputs are always bypassed with diodes, as shown in Fig. 11.4. The permissible current through these diodes is also specified in the specifications.

The parameters of modern CMOS chips (complementary MOS chips) are approaching ideal. First, the typical static power dissipation of a CMOS chip due to leakage currents is on the order of 10 nW per gate. Active (or dynamic) power dissipation depends on the power supply voltage, switching frequency, output load and rise time of the input signal, but its typical value for one valve at a frequency of 1 MHz and a load with a capacity of 50 pF does not exceed 10 mW.

Secondly, although the signal propagation delay time in CMOS gates is not zero, it is quite small. Depending on the power supply voltage, the signal propagation delay for a typical element is in the range from 4 to 8 ns.

Third, the rise and fall times are controlled and represent linear rather than step functions. Typically they are 20-40% larger than the signal propagation delay time.

Finally, a typical noise immunity value is approximately 45% of the output signal amplitude.

Another important factor in favor of CMOS chips is their low cost, especially when used in portable equipment powered by low-power batteries.

Power supplies in systems built on CMOS chips can be low-power and, as a result, inexpensive. Due to low power consumption, the power subsystem can be simpler and therefore cheaper. There is no need for radiators and fans due to low power dissipation. Continuous improvement of technological processes, as well as an increase in production volumes and expansion of the range of manufactured CMOS microcircuits lead to a reduction in their cost.

There are many series logic chips CMOS structures. The first of them was the K176 series, then K561 (CD4000AN) and KR1561 (CD4000BN), but greatest development functional series were obtained in the KR1554 (74ASxx), KR1564 (74HCxx) and KR1594 (74ACTxx) series.

The functional series of modern CMOS microcircuits of the KR1554, KR1564 and KR1594 series contain full-function equivalents of the TTLSH series KR1533 (74ALS) and K555 (74LS) microcircuits, which completely coincide both in the functions performed and in the pinout of A.L. Odinets, Minsk, E-mail: [email protected](pinout). Modern CMOS microcircuits, compared to their prototypes, the K176 and K561 series, consume significantly less dynamic power and are many times faster than them.

To simplify circuit solutions, CMOS series have been developed with both the input threshold voltage of TTL levels (KR1594 and some others) and CMOS levels (KR1554, KR1564 and some others). The operating temperature range for general-purpose microcircuits is within -4О...+85°С and -55... + 125°С for microcircuits special application. Table 1 shows a comparison of the input and output characteristics of CMOS and TTL chips.

Characteristics of CMOS chips

The purpose of this section is to give the developer digital systems necessary information about how digital microcircuits of the CMOS structure work and how they behave when exposed to various control signals. Quite a lot has been written about the design and production technology of CMOS microcircuits, so today we will consider only their circuit design features.

Table 1. Comparison electrical parameters CMOS and TTLSH circuits

The basic CMOS circuit is the inverter shown in Fig. 1. It consists of two field-effect transistors operating in enrichment mode: with a P-type channel (upper) and an N-type channel (lower). The power pins are designated as follows: VDD or Vcc for the positive pin and Vss or GND for the negative pin. The designations VDD and Vcc are borrowed from conventional MOS circuits and symbolize the source and drain power supplies of the transistors. They do not apply directly to CMOS circuits, since the power pins are the sources of both complementary transistors. The designations Vss or GND are borrowed from TTL circuits, and this terminology is retained for CMOS chips. Next, the designations VCC and GND will be indicated.

Rice. 1. The simplest CMOS inverter

The logic levels in a CMOS system are Vcc (logic "1") and GND (logic "0"). Since the current flowing in the “on” MOS transistor creates virtually no voltage drop across it, and the input resistance of the CMOS gate is very high (the input characteristic of the MOS transistor is mainly capacitive and looks similar to its current-voltage characteristic with a resistance of 1012 Ohms, shunted by a 5 pF capacitor ), then the logic levels in the CMOS system will be almost equal to the voltage of the power supply.

We suggest looking at the characteristic curves of MOSFETs to get an idea of ​​how rise and fall times, propagation delays, and power dissipation will change with changes in power supply voltage and load capacitance.

In Fig. Figure 2 shows the characteristic curves of N-channel and P-channel field-effect transistors operating in enrichment mode.

A number of important conclusions follow from these characteristics. Consider the curve for an N-channel transistor with a Gate-Source voltage equal to VGS = 15V. It should be noted that for a constant control voltage VGS, the transistor behaves as a current source at values ​​of VDS (Drain-Source voltage) greater than VGS-VT (MOS transistor threshold voltage). For values ​​of VDS less than VGS-VT, the transistor behaves essentially like a resistor.

It should also be noted that at lower values ​​of VGS the curves have a similar character, with the exception that the value of IU (Drain-Source current) is much smaller, and, in fact, IU increases in proportion to the square of VGS. The P-channel transistor has almost identical, but complementary (complementary) characteristics.

When driving a capacitive load using CMOS elements, the initial change in voltage applied to the load will be linear, due to the "current" characteristic in the initial section, obtained by rounding off the dominant resistive characteristic when the VDS value differs little from zero. In relation to the simplest CMOS inverter shown in Fig. 1, as the voltage VDS decreases to zero, the output voltage V0UT will tend to GND, depending on which transistor is open: P-channel or N-channel.

If Vcc, and therefore VGS, is increased, the inverter must develop a larger voltage amplitude across the capacitor. However, for the same voltage increment, the load capacity of 1U increases sharply as the square of VGS, and therefore the rise times and propagation delays shown in Fig. 3, decrease.

Thus, it can be seen that for a given design, and therefore a fixed value of load capacitance, increasing the power supply voltage will improve system performance. Increasing Vcc will not only improve the performance, but also the dynamic power dissipated by the inverter, which has two components. Firstly, this is the power consumed to recharge the load capacity. This component of power dissipation is proportional to the load capacitance, the inverter switching frequency and the square of the voltage drop across the load.

Rice. 2. Dependence of output current Ids on output voltage for three different meanings supply voltage Voo and initial Gate-Source bias Vos

The second component of the power dissipated by the inverter is due to the fact that every time the circuit switches from one state to another, at VCC>2VT, a through current Isw briefly appears, flowing from Vcc to GND through two simultaneously partially open output transistors.

Since the threshold voltages of the transistors do not change with increasing Vcc, the input voltage range within which the upper and lower transistors are simultaneously in a conducting state increases with increasing Vcc. At the same time, a larger value of Vcc provides larger values ​​of control voltages VGS, which also lead to an increase in current Isw. However, if the rise time of the input signal were zero, then there would be no through current through the output transistors. Obviously, the rise and fall times of the edges of the input signal must have minimum value to reduce power dissipation.

Let's consider how the transfer characteristics of the inverter depend on the supply voltage Vcc(pnc. 5). Let’s agree to assume that both transistors have identical, but complementary (mutually complementary) characteristics and threshold voltages. If Vcc is less than the 2VT threshold voltage, none of the transistors can be turned on and the circuit is in closed state. In Fig. Figure 5a shows a situation where the power supply voltage exactly matches the threshold voltage. In this case, the circuit should operate with 100% hysteresis. However, this is not exactly hysteresis, since both output transistors are turned off and the output voltage is maintained across the gate capacitances downstream of the circuits. If Vcc is within one or two threshold voltages (Fig. 56), the amount of “hysteresis” decreases as Vcc approaches a value equivalent to 2VT (Fig. 5c). At a voltage Vcc equivalent to two threshold voltages, there is no “hysteresis”, and there is also no through current through the transistors at switching moments. When the value of Vcc exceeds two threshold voltages, the transfer characteristic curves begin to round off (Fig. 5d). When Vm passes through the region where both transistors are open, the currents flowing in the transistor channels create voltage drops, giving a rounding of the characteristics.

When considering a CMOS system for noise immunity, it is necessary to keep in mind at least two characteristics: noise immunity and noise margin.

Rice. H. Measuring rise and fall times and propagation delays in a CMOS system

Modern CMOS circuits have a typical noise immunity value of 0.45Vcc. This means that a false input signal that differs from Vcc or GND by an amount equal to 0.45Vcc or less will not propagate through the system as a faulty logic level. Typically such a signal does not change the output state logic element. In a flip-flop, for example, a false input clock pulse with an amplitude of 0.45Vcc will not change its state.

This does not mean that no signal will appear at the output of the circuit at all. In fact, as a result of the influence of the interference signal, an output signal will appear at the output of the inverter, but it will be weakened in amplitude. As it propagates through a digital system, the signal will be weakened further by subsequent circuits until it disappears completely.

Rice. 4. Guaranteed margin of noise immunity of the CMOS circuit in the temperature range as a function of the supply voltage V

The CMOS chip manufacturer also guarantees a 1V noise margin over the entire range of supply voltages and temperatures and for any combination of inputs. This is just a deviation of the noise immunity characteristic. In other words, from this characteristic it follows that in order for the circuit’s output signal, expressed in volts, to be within 0.1 Vcc of the value of the corresponding logic level (“zero” or “one”), the input signal must not exceed the value 0 ,1 Vcc plus 1V above ground level or below power level. Graphically this situation is shown in Fig. 4.

For standard TTL circuits, for example, the noise margin is 0.4V (Fig. 6).

Analysis of the application features of CMOS chips

Fig.5 Transfer characteristics for different values ​​of supply voltage Vcc

IN this section Various situations that arise when developing digital systems using CMOS chips are considered: unused inputs, parallel connection of elements to increase load capacity, wiring of data buses, coordination with logic elements of other families.

Rice. 6. Guaranteed values ​​of the logic level voltage range for TTL circuits over a temperature range as a function of supply voltage V

Unused pins or, more simply put, unused inputs should not be left unconnected. Due to the very high input resistance (1012 ohms), the floating input can drift between logic zero and logic one, creating unpredictable circuit output behavior and associated system problems. All unused inputs must be connected to the power rail, "common" wire, or another usable input. The choice of solution is not accidental, since it is necessary to take into account the possible impact on the output load capacity of the circuit. Consider, for example, a four-input 4I-NOT gate, used as a two-input 2I-NOT logic gate. Its internal structure is shown in Fig. 7.

Let inputs A and B be unused inputs. If unused inputs are connected to fixed high logical level, then inputs A and B are connected to the power bus to allow the remaining inputs to operate. This will turn on the lower A and B transistors and turn off the corresponding upper A and B. In this case, no more than two upper transistors can be turned on at the same time. However, if inputs A and B are connected to input C, the input capacitance triples, but each time input C goes to logic zero, the top transistors A, B, and C turn on, tripling the value of the maximum output current at logic one. If input D also receives a logic zero level, all four upper transistors are turned on. Thus, connecting unused inputs of an NAND element to the power bus (OR-NOT to the “common” wire) will turn them on, but connecting unused inputs to other used inputs guarantees an increase in the output flowing current of the logical “one” level, in the case of an element AND-NOT (or the output inflowing current at the level of logical “zero” in the case of an OR-NOT element).

For transistors connected in series, the output current does not increase. Given this circumstance, a multi-input logic element can be used to directly control a powerful load, for example, a relay coil or an incandescent lamp.

Depending on the type of logic element, combining inputs guarantees an increase in the load capacity for either the leaking or sinking currents, but not both at the same time. In order to guarantee an increase in the two output currents, it is necessary to connect several logic elements in parallel (Fig. 8). In this case, an increase in load capacity is achieved due to parallel connection several chains of transistors (Fig. 7), which increases the corresponding output current.

Rice. 7. Four-input logical element 4I-NOT, part of the KR1561LA1 microcircuit

There are two main methods for wiring data buses. The first way is parallel connection conventional CMOS buffer elements (for example, K561LN2). And the second, most preferable, method is to connect elements with three output states.

The article was provided by the editors of the Electronics magazine. You can read other articles from the Electronics magazine

The vast majority of modern logic chips, including processors, use CMOS circuitry.

Story

Early CMOS circuits were very vulnerable to electrostatic discharge. Now this problem has been largely solved, but when installing CMOS chips, it is recommended to take measures to remove electrical charges.

For the manufacture of gates in CMOS cells based on early stages aluminum was used. Later, in connection with the advent of the so-called self-combined technology, which involved the use of a gate not only as a structural element, but at the same time as a mask when obtaining drain-source regions, polycrystalline silicon began to be used as a gate.

Technology

Scheme 2I-NOT

For example, consider a 2I-NOT gate circuit built using CMOS technology.

• If both inputs A and B are supplied high level, then both transistors at the bottom of the diagram are open, and both top transistors are closed, that is, the output is connected to ground.
• If you apply at least one of the inputs low level, the corresponding transistor will be open at the top and closed at the bottom. Thus, the output will be connected to the supply voltage and disconnected from ground.

There are no load resistances in the circuit, so in a static state, only leakage currents flow through the CMOS circuit through the off-circuit transistors, and the power consumption is very low. When switching Electric Energy is spent mainly on charging the capacitances of the gates and conductors, so the power consumed (and dissipated) is proportional to the frequency of these switchings (for example, the processor clock speed).

Series of foreign-made CMOS logic chips

Series of domestically produced CMOS logic chips

• On CMOS transistors (CMOS):
  • 164, 176, 561 and 564 correspond to the 4000 series, but 164 and 176 only have 9V power supply;
  • 1554 - 74AC series;
  • 1561 - 4000B series;
  • 1564 - 74HC series;
  • 1594 - 74ACT series;
  • 5564 - 74HCT series;

CMOS (complementary metal-oxide-semiconductor structure) is a technology for constructing electronic circuits. In a more general case - CMDC (with a metal-insulator-semiconductor structure). A distinctive feature of CMOS circuits compared to bipolar technologies (TTL, ESL, etc.) is very low power consumption in static mode (in most cases, it can be assumed that energy is consumed only during state switching )

The vast majority of modern logic chips, including processors, use CMOS circuitry. CMOS technology uses insulated gate field effect transistors with channels of different conductivity.

In devices based on CMOS chips, anti-bounce measures known from experience with TTL chips, for example, turning on a static trigger on two NAND or NOR elements. However, the extremely high input impedance of CMOS chips (on the order of hundreds and thousands of megaohms) and relatively high output impedance (hundreds of ohms to one kiloohm) make it possible to simplify the debounce circuits by eliminating resistors. A variant of the circuit is a device assembled using just one non-inverting logic element.

Here a few words should be said about non-inverting logic elements of the CMOS series. Most of the logic elements in these series are inverting. As mentioned above, microcircuits containing the letters “PU” in their designation serve to match CMOS microcircuits with TTL microcircuits. For this reason, their output currents, when supply voltage is applied to their outputs or the outputs are connected to a common wire in the device according to circuits, can reach many tens of milliamps, which negatively affects the reliability of the devices and can serve as a powerful source of interference. The high input impedance of CMOS microcircuits allows, in some cases, to do without active elements for debouncing at all.

The most promising series are those made on complementary MOS transistors (CMOS) (K176, K564, etc.). They do not have load resistors, and MOS transistors with different electrical conductivities of the channels act as switches. When the gate voltage is greater than the threshold, for transistors with a channel certain type the corresponding transistor is unlocked and the other is locked. At another value greater than the threshold value for transistors with electrical conductivity of the opposite type, the unlocked and locked transistors change places. Such structures operate successfully when the power supply voltage varies over a wide range (from 3 to 15 V), which is unattainable for logic elements that include resistors. In static mode, with high load resistance, CMOS logic elements consume virtually no power.

They are also characterized by: stability of input signal levels and its small difference from the power source voltages; high input and low output resistance; good noise immunity; ease of coordination with microcircuits of other series.

CMOS logic gates performing the 3 NAND function. It uses induced channel transistors. Transistors VT1-VT3 have a -type channel and are open when the gate voltage is close to zero. Transistors have an -type channel and are open at gate voltages greater than the threshold value.

When there is a zero input signal at at least one of the inputs of the logical element, one of the transistors is open and the output voltage is equal to E. And only if there is a logical one signal at all inputs (usually equal to E), all transistors VT1 are closed and tier turned on transistors are open. Output voltage equal to the common bus potential (logical 0). Thus, the combination of tiered connection of transistors with channels having one type of electrical conductivity and parallel connection of transistors with channels of a different type of electrical conductivity made it possible to implement the NAND function.

If groups of tiered and parallel-connected transistors are swapped, then an element that performs the function will be realized. It works similar to the previous one. Transistors are open if their gates are logical 1, and are locked when input signals are logical 0.

From the considered circuits it is clear that in static mode one of the transistors connected in series is always closed, and the other is open. Since a closed transistor has a high resistance, the current in the circuit is determined only by small values ​​of leakage currents and the microcircuit practically does not consume electrical power.

A circuit is usually used as a basic inverter installed at the LE input. To prevent breakdown of the oxide film under the gates of MOS transistors, the inverter circuit is usually supplemented with diodes that perform protective functions. The time constant of these components is about 10 ns. Therefore, their introduction does not significantly change dynamic characteristics logical elements. When entering the input circuit static stress of one polarity or another, the corresponding diodes open and short-circuit a source of static charge to the power supply circuit. The resistor, which, together with the barrier capacitances of the diodes, forms an integrating circuit, reduces the rate of increase in voltage at the gate to a value at which diodes VD2, VD3 have time to open.

If the voltage source has low internal resistance, then a large forward current will flow through the diode. Therefore, when turning on equipment with such logic elements, the supply voltage must be supplied before the input signal, and when turning off, vice versa. In cases where some reduction in performance is acceptable, resistors can be included in the input circuit to limit the input current level.

In a number of microcircuits, to increase the steepness of the transfer function and increase the load capacity, one or two additional inverters are connected to the output of the inverter of the logic element. Transistors of the additional inverter have increased power. Due to them, the resistance of the channels of the open output transistors of the inverter is reduced from kOhm to kOhm. These output resistance values ​​make it possible not to introduce current-limiting resistors into the output circuits to protect against short circuits at the output.

In CMOS logic elements, elements with three stable states are extremely simply implemented. To do this, two complementary transistors controlled by inverse signals are connected in series with the inverter transistors. If the transistors are closed when signals are supplied, then the output resistance of the inverter has great importance(the inverter is in the third high impedance state).

The third state is present in individual microcircuits, for example, in logic elements of the type, as well as in complex functional units of the CMOS series.

Matching TTL logic elements with CMOS logic elements can be done in several ways:

1) power CMOS logic elements with low voltages, at which the signals of TTL logic elements switch the transistors of CMOS logic elements;

2) use TTL logic elements with an open collector, the output circuit of which includes a resistor connected to an additional voltage source;

3) use level converter microcircuits when matching CMOS series with TTL series and when matching TTL series with CMOS series).

Increase if necessary output power Parallel connection of several microcircuits is allowed. To suppress interference in the power circuit between the power buses, turn on electrolytic capacitor capacitance and parallel to it are ceramic capacitors with a capacitance per housing. The latter are connected directly to the outputs of the microcircuits. The load capacitance should generally not exceed. If the load capacitance is larger, an additional resistor is installed in series with the output, limiting its overdischarge current. If there are voltage surges in the input signal, a limiting resistor with a nominal value of up to 10 kOhm can be connected in series with the LE input. Unused LE inputs must be connected to the power supply buses or connected in parallel with the connected inputs. Otherwise, breakdowns of the dielectric under the gate and malfunction due to the strong influence of interference are possible.

Short-circuiting of the output terminals of microcircuits is allowed at low supply voltage.

During storage and installation, beware of static electricity. Therefore, during storage, the terminals are electrically connected to each other. Their installation is carried out with the supply voltage turned off, and the use of bracelets is mandatory, with the help of which the body of the electricians is connected to the ground.

CMOS-series logic elements are widely used in the construction of cost-effective digital devices low and medium speed. In the future, as their manufacturing technology improves, they can compete with TTL logic elements when creating high-speed devices.

Typically, when designing probes and calibrators, short pulse generators are used to produce a signal with a wide and uniform spectrum. Such a signal allows you to quickly check radio equipment cascades, both low-frequency (LF) and high-frequency (HF). Moreover, the shorter the pulse duration, the better - the spectrum is wider and more uniform.

As a rule, such generators consist of two main components: the rectangular pulse generator itself and the short pulse shaper. Meanwhile, you can do without a special driver, since it is already present in the logical element of the CMOS structure microcircuit.

Let's look at the diagram

Figure 4 - RC generator

Figure 4 shows a well-known RC oscillator operating in in this case at a frequency of about 1000 Hz (it depends on the ratings of parts R1, C1). A low-frequency rectangular signal is supplied from the output of element DD1.2 (pin 4) through the R2C3 chain to the variable resistor R4 - it smoothly regulates the amplitude of the signal supplied to the unit being tested.

The way out high frequency signal(short pulses) is performed somewhat unusually - the signal is removed from the variable resistor R3, connected to the power circuit of the microcircuit. By moving the slider of this resistor, the level of the output high-frequency signal is smoothly adjusted.

Let's consider the principle of operation of such a driver using a simplified diagram of the logical element of the CMOS structure shown in Figure 5.

Figure 5 - Simplified diagram of a CMOS gate structure

Its basis is two field-effect transistors connected in series with an insulated gate and different types of channel conductivity. If resistor R1 is connected in series with the transistors, and rectangular pulses U1 are applied to the input of the element, the following will happen (Fig. 3). Due to the fact that the duration of the pulse front cannot be infinitesimal, as well as due to the inertia of the transistors, at the moment the front acts, a moment will come when both transistors will be in the open state. The so-called through current will flow through them, the value of which can range from units to tens of milliamps, depending on the type of microcircuit and the voltage of the power source. Short voltage pulses U2 will be formed across the resistor. Moreover, both at the time of the front and recession.

In other words, the frequency of the original pulses will double.

The resistance of the resistor should not be high in order to avoid disruption of the operating mode of the microcircuit elements. This means that a low-impedance load with a resistance of 50...75 Ohms can be connected to the high-frequency output.

For the considered generator, the maximum amplitude of pulses at the high-frequency output is 100...150 mV, and the current consumed from the power source does not exceed 1.6 mA. The generator is designed for use when testing AF amplifiers, three-program loudspeakers, and radio receivers on the LW and MW bands.

CMOS structures

Field-effect transistor - semiconductor device, through which a flow of main charge carriers flows, regulated by a transverse electric field, which is created by a voltage applied between the gate and drain or between the gate and source.

Since the operating principle of field-effect transistors is based on the movement of the main charge carriers of the same type (electrons or holes), such devices are also called unipolar, thereby contrasting them with bipolar ones.

Field-effect transistors are classified into devices with a control p-n junction and with an insulated gate, the so-called MOS (metal-dielectric-semiconductor) transistors, which are also called MOS (metal-oxide-semiconductor) transistors, and the latter are divided into transistors with a built-in channel and devices with an induced channel.

The main parameters of field-effect transistors include: input resistance, internal resistance of the transistor, also called output, steepness of the drain-gate characteristic, cut-off voltage and some others.

A field-effect transistor with a control p-n junction is a field-effect transistor in which a semiconductor plate, for example n-type, has electrodes (drain and source) at opposite ends, with the help of which it is connected to the controlled circuit. Control circuit connects to the third electrode (gate) and forms an area with a different type of conductivity, in this case p-type.

The power source included in the input circuit creates a reverse voltage at a single p-n junction. The source of amplified oscillations is also included in the input circuit. When the input voltage changes, the reverse voltage at the p-n junction changes, and therefore the thickness of the depletion layer (n-channel) changes, that is, the cross-sectional area of ​​the region through which the flow of the main charge carriers passes. This area is called a channel.

A distinctive feature of the CMOS structure compared to other MOS structures (N-MOS, P-MOS) is the presence of both n- and p-channel field-effect transistors; as a result, CMOS circuits have more high speed actions and lower energy consumption, however, they are characterized by a more complex manufacturing process and lower packaging density.